In-Memory Computing Circuit for Neural Network Power Reduction
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Solution Overview
Problem
Current neural network processing technologies face inefficiencies in power consumption and data movement due to the separation of computation and memory units, leading to high power usage and complex hardware structures in digital computers.
Innovation Solution
The implementation of an in-memory computing circuit with an analog crossbar array and digital-to-analog converters, where memory cells store weights and perform multiply-accumulate operations directly, reducing the need for extensive data movement and power consumption by integrating memory and computation units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital computation units and memory units are separated, then computational flexibility is improved, but power consumption increases and data movement becomes complex
Solution Approach 1:
The patent merges memory units and computation units into an integrated in-memory computing circuit. Memory cells store weights while crossbar arrays perform MAC operations directly on stored data, eliminating the need to move data between separate memory and computation units. This integration reduces power consumption associated with data movement while maintaining computational capability through the unified architecture.
2Adaptability or versatility
If digital computation units and memory units are separated, then computational flexibility is improved, but hardware structure becomes complex
Solution Approach 1:
The patent merges memory units and computation units into an integrated in-memory computing circuit. Memory cells store weights while crossbar arrays perform MAC operations directly on stored data, eliminating the need to move data between separate memory and computation units. This integration reduces power consumption associated with data movement while maintaining computational capability through the unified architecture.
3Use of energy by moving object
If in-memory computing is implemented, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs calibration techniques to adjust and optimize the precision parameters of the in-memory computing circuit. By calibrating the weight values stored in memory cells and adjusting operational parameters of the crossbar arrays, the system compensates for manufacturing variations and achieves accurate neural network computations despite inherent precision limitations in analog or in-memory computing hardware.
Data Source
AI summary
A neural network device includes a shift register circuit, a control circuit, and a processing circuit. The shift register circuit includes registers configured to, in each cycle of cycles, transfer stored data to a next register and store new data received from a previous register to a current register. The control circuit is configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order. The processing circuit, includes crossbar array groups that receive input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, is configured to accumulate and add at least some operation results output from the crossbar array groups in a preset number of cycles to obtain an output activation in an output feature map.