In-Memory Processing Circuit for Neural Network Efficiency
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Solution Overview
Problem
Neural network processing faces inefficiencies due to increased computational demands and memory access frequency as data complexity and connectivity rise, leading to performance issues and miniaturization challenges, particularly in the need for efficient hardware architectures to handle multiply-accumulate operations at low power and high speed.
Innovation Solution
An in-memory processing apparatus and method utilizing a memory cell array, sampling circuit, and processing circuit that charges capacitors based on column currents, performs time-digital conversion, and generates trigger pulses to determine quantization levels, reducing the need for analog-to-digital converters and improving power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional von Neumann architecture is used for neural network processing, then data can be stored in memory, but computational efficiency deteriorates due to frequent memory access and increased computational demands
Solution Approach 1:
The patent merges memory storage and computational functions into a single integrated circuit. Memory cells are configured to perform multiply-accumulate operations directly during readout, eliminating the need for separate computational units and reducing data transfer between memory and processor. This integration directly addresses the contradiction by enabling efficient computation without additional power consumption for separate processing hardware.
Solution Approach 2:
The patent replaces traditional electronic signal processing with analog current-based computation. Memory cells operate by converting digital input signals into analog currents that flow through column lines, where the current sum directly represents the computational result. This substitution eliminates the need for complex digital arithmetic operations and reduces power consumption associated with high-speed digital processing.
2Adaptability or versatility
If computational complexity and connectivity increase in neural networks, then processing capability improves, but hardware architecture complexity increases requiring more resources
Solution Approach 1:
The patent designs memory cells to serve multiple functions: storage, computation, and output generation. Each memory cell can perform multiply-accumulate operations during readout, and the same hardware structure handles both data storage and processing tasks. This multi-functionality allows the system to handle increased computational complexity without adding corresponding hardware complexity, as the same memory array structure supports all operations.
Solution Approach 2:
The patent segments the neural network processing into column-based current summing operations. Each column line independently processes computations for specific neuron outputs, allowing parallel processing across multiple columns. This segmentation enables the system to handle complex computations by distributing them across multiple simple, identical units rather than requiring a single complex processor.
3Speed
If multiply-accumulate operations are performed at high speed, then processing throughput improves, but power consumption increases
Solution Approach 1:
The patent employs periodic sampling operations where memory cells are readout at specific timing intervals controlled by sampling circuits. The periodic nature of these operations allows the system to achieve high processing throughput through efficient batch operations rather than continuous high-speed processing. The timing control enables synchronized current summing that completes computations in discrete cycles, reducing overall power consumption while maintaining high effective processing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances neural network processing efficiency by reducing power consumption and circuit size through on-chip time-digital conversion, effectively handling complex computations within the memory array, thereby addressing performance and miniaturization challenges.
Implementation Method 1
a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines
Implementation Method 2
a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse
Data Source
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AI summary
An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.