Inner Bump Assembly Mode Definition for Wafer-Level Package Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer-level package (WLP) devices face challenges in achieving high routing density without the use of costly stacked vias, which are often avoided due to extra manufacturing costs, and increasing pitch size is undesirable as it increases both cost and size.
Innovation Solution
The semiconductor device configuration includes an integrated circuit chip with inner and outer bump assemblies, where the connection between them defines the chip's state of operation, eliminating the need for external circuit board routing and reducing PCB layout complexity and costs by using mode sensing and selector functionality to select adjustable parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked vias are used to achieve high routing density, then routing density is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the routing density function from the PCB stacked vias and relocates it to the chip-level bump assembly connections. By defining operational modes through inner bump connections to outer bumps without requiring PCB stacked vias, the solution achieves high routing density at the chip level while eliminating the costly PCB manufacturing process
Solution Approach 2:
The patent transitions from two-dimensional PCB routing to three-dimensional chip-level bump assembly connections. By utilizing vertical stacking of bump assemblies (inner bumps connected to outer bumps) and defining operational modes through these connections, the solution achieves high routing density in the vertical dimension rather than requiring dense horizontal PCB routing
2Ease of manufacture
If pitch size is increased to simplify routing, then ease of manufacture is improved, but device size and cost increase
Solution Approach 1:
The patent moves the routing complexity resolution from the two-dimensional PCB plane to the three-dimensional chip-level bump assembly structure. By using vertical bump stacking and inner-outer bump connections to define operational modes, the solution simplifies PCB layout without increasing device pitch size
Solution Approach 2:
The chip's bump assembly connection configuration automatically defines its operational modes without requiring external PCB routing intervention. The inner bump connections to outer bumps self-determine the operational state, eliminating the need for complex external circuit board routing
Data Source
AI summary
Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an implementation, the semiconductor device, which may be a wafer-level (chip-scale) package semiconductor device, includes an integrated circuit chip, a plurality of outer bump assemblies disposed on the chip, and one or more inner bump assemblies disposed on the chip so that the inner bump assemblies are at least partially surrounded by the outer bump assemblies. At least one of the inner bump assemblies is configured to be connected to a selected outer bump assembly to cause the integrated circuit chip to have a desired state of operation.