Inner Gate Spacer Profile for Scaled MOSFET Reliability
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Solution Overview
Problem
The scale-down of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability and electrical characteristics to meet increasing demand for smaller pattern sizes and reduced design rules.
Innovation Solution
The semiconductor device design includes a substrate with a channel pattern of spaced semiconductor patterns, a source/drain pattern, a gate electrode with an inner gate electrode and spacer, and an inner high-k dielectric layer, where the inner gate spacer has a center portion and edge portions with varying thicknesses, optimizing the gate electrode's structure for improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for smaller pattern sizes, then the pattern size and design rule are reduced, but the operational properties of the semiconductor devices deteriorate
Solution Approach 1:
The inner gate spacer is designed with non-uniform thickness, having a first thickness in a first region and a second thickness in a second region, where the thickness varies along the channel direction. This local variation in spacer thickness allows optimization of electrical characteristics at different positions within the transistor, improving overall device performance while maintaining scaled dimensions
Solution Approach 2:
The invention changes the thickness parameter of the inner gate spacer from uniform to non-uniform, with the first thickness being greater than the second thickness. This parameter modification optimizes the gate control over the channel region, enhancing operational properties despite the reduced overall device size
2Ease of manufacture
If the inner gate spacer has uniform thickness, then the structure is simpler to manufacture, but the gate electrode formation uniformity and electrical characteristics are compromised
Solution Approach 1:
The inner gate spacer exhibits different thickness characteristics in different regions: a first thickness in the first region and a second thickness in the second region. This local quality variation enables precise control of gate electrode formation and electrical characteristics while maintaining compatibility with existing manufacturing processes
Data Source
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AI summary
A semiconductor device comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between first and second semiconductor patterns among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source/drain pattern, wherein the inner gate spacer includes a center portion and an edge portion, the center portion has a first thickness in a second direction, the edge portion has a second thickness in the second direction, the first thickness is greater than the second thickness, the first and second semiconductor patterns are adjacent to each other in a third direction.