Inner Outer Code Generator Volatile Memory Error Correction
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Solution Overview
Problem
Volatile memory technologies, such as DRAM, face challenges in maintaining data integrity due to charge leakage, leading to data loss and errors without persistent refreshes, and existing error correction methods are inadequate for detecting and correcting multiple bit errors effectively.
Innovation Solution
A memory controller system that generates and updates both inner and outer correction codes, using error checking and correction codes (ECC), parity codes, CRC, Hamming codes, BCH codes, LDPC codes, or Reed-Solomon codes, to detect and correct single and multiple bit errors, with a memory scrubber operating in the background to correct errors during refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used in volatile memory, then single bit errors can be corrected, but multiple bit errors cannot be effectively detected and corrected
Solution Approach 1:
The correction code is divided into two segments: inner correction codes (e.g., ECC) for individual data blocks and outer correction codes for multiple data blocks. This segmentation enables the system to handle both single bit errors within blocks and multiple bit errors across blocks, resolving the limitation of conventional single-layer correction methods
Solution Approach 2:
The correction structure implements a nested hierarchy where inner correction codes are embedded within each data block, and outer correction codes encompass multiple data blocks. This nested arrangement allows progressive error correction, first attempting inner code correction and then outer code correction for remaining errors, thereby achieving multiple bit error correction without excessive complexity
2Reliability
If refresh cycles are performed frequently to prevent charge leakage, then data integrity is maintained, but system productivity decreases
Solution Approach 1:
Correction codes are generated and stored in advance during the write operation, before the actual data storage in volatile memory. This preliminary preparation allows the memory controller to quickly verify and correct errors during refresh cycles without performing complex correction calculations, thereby maintaining data integrity while minimizing the time spent on correction operations and preserving system throughput
Solution Approach 2:
The memory system performs self-correction of errors during normal refresh operations. The correction codes enable the memory controller to automatically detect and correct errors without requiring external intervention or complex processing, allowing refresh cycles to maintain data integrity with minimal impact on productivity
Data Source
AI summary
A system includes a volatile memory to store data and a memory controller to manage the data in the volatile memory. The memory controller includes an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory. An outer code generator generates an outer correction code based on the plurality of blocks of the data. The memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory.