Inner Spacer Air-Gap Structure for Low-Capacitance Multi-Gate Transistors
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Solution Overview
Problem
As semiconductor technology advances to sub-10 nm technology nodes, existing multi-gate transistors face challenges with increased stray capacitance due to etching loss of low-k materials in inner spacers, leading to reduced distance between gate structures and source/drain contacts, which hampers switching speed, power consumption, and coupling noise.
Innovation Solution
The introduction of inner spacers with air gaps and a high-k insulating layer that insulates air gaps from gate structure materials, reducing effective dielectric constant and controlling spacer thickness, shape, and location to minimize capacitance, specifically reducing gate-to-drain and gate-to-source capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-k materials are used in inner spacers to reduce capacitance, then gate-to-drain and gate-to-source capacitance decrease, but etching loss occurs causing reduced distance between gate structures and source/drain contacts
Solution Approach 1:
The patent changes the dielectric constant parameter of the inner spacer material from low-k to high-k materials (such as silicon nitride or silicon oxynitride). This parameter change resolves the contradiction by providing etching resistance while still allowing capacitance control through adjusted spacer thickness, thereby maintaining manufacturing precision without sacrificing energy loss reduction
Solution Approach 2:
The patent employs composite material structures where high-k dielectric materials are combined with carefully controlled spacer geometries. The high-k material provides etching resistance, while the composite structure (material + geometric configuration) achieves the dual goal of reduced stray capacitance and maintained dimensional precision
2Loss of energy
If inner spacer thickness is reduced to minimize capacitance, then gate-to-drain and gate-to-source capacitance decrease, but control over spacer dimensions becomes difficult
Solution Approach 1:
The patent changes the material parameter from low-k to high-k dielectric materials, which have superior etching resistance properties. This enables precise control of thin spacer dimensions during fabrication while still achieving the desired capacitance reduction through controlled thickness
Solution Approach 2:
The high-k dielectric material acts as an intermediary that enables the formation of precisely controlled thin spacers. The material's properties serve as a mediator between the conflicting requirements of thin dimensions (for low capacitance) and fabrication control (for manufacturing precision)
3Productivity
If transistor dimensions are scaled down to sub-10 nm nodes to increase device density, then production efficiency increases, but stray capacitance effects become more significant
Solution Approach 1:
The patent applies parameter changes by transitioning from low-k to high-k dielectric materials in inner spacers, which fundamentally alters the electrical characteristics to reduce stray capacitance. This enables continued scaling to sub-10 nm nodes while mitigating the increasing capacitance effects that would otherwise limit further density improvements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances switching speed, decreases power consumption, and improves device uniformity and yield rate by effectively reducing stray capacitance and maintaining precise control over spacer dimensions.
Implementation Method 1
reducing effective dielectric constant and controlling spacer thickness, shape, and location to minimize capacitance
Implementation Method 2
a high-k insulating layer that insulates air gaps from gate structure materials
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.