Multi-Gate Inner Spacer Air-Gap Layout for Gate Fringe Capacitance
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Solution Overview
Problem
As semiconductor technology advances to sub-10 nm technology nodes, existing low-k materials in inner spacers for multi-gate transistors face etching loss issues during the replacement gate process, leading to increased stray capacitance and reduced distance between gate and source/drain contacts, which hampers switching speed, power consumption, and noise performance.
Innovation Solution
The introduction of inner spacers with air gaps and a high-k insulating layer that insulates air gaps from gate structure materials, reducing effective dielectric constant and controlling spacer thickness, shape, and location to minimize capacitance, specifically reducing gate-to-drain and gate-to-source capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k materials are used in inner spacers, then stray capacitance is reduced, but etching loss occurs during replacement gate process leading to increased distance between gate and source/drain contacts
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the inner spacer and the gate structure. This sacrificial layer is selectively removed during processing to create a cavity, which is then filled with low-k material. The low-k material is subsequently exposed by removing portions of the gate structure, achieving low stray capacitance without etching loss of the inner spacer itself.
Solution Approach 2:
The inner spacer is formed with precise dimensions and material composition before the gate structure is fully assembled. The sacrificial layer is positioned and configured in advance to protect the inner spacer during subsequent processing steps, ensuring the distance between gate and source/drain contacts is maintained before the low-k material is exposed.
2Object-affected harmful factors
If inner spacer thickness is reduced to minimize capacitance, then gate-to-drain and gate-to-source capacitance decrease, but device uniformity and yield rate are compromised
Solution Approach 1:
The patent utilizes materials with different etching selectivities and deposition characteristics to enable precise control of the inner spacer thickness. By selecting specific material combinations and processing parameters, the inner spacer can be formed with controlled thickness that minimizes capacitance while maintaining sufficient structural integrity and uniformity across devices.
Solution Approach 2:
The patent replaces direct mechanical contact and physical support relationships with field-based interactions and sacrificial layer protection. The inner spacer's structural role is maintained through the sacrificial layer framework rather than relying solely on the spacer's mechanical strength, enabling thinner designs with improved capacitance characteristics while preserving device uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances switching speed, decreases power consumption, and reduces coupling noise by effectively managing stray capacitance while maintaining device uniformity and yield rate.
Implementation Method 1
reducing effective dielectric constant and controlling spacer thickness, shape, and location to minimize capacitance
Implementation Method 2
a high-k insulating layer that insulates air gaps from gate structure materials
Data Source
AI summary
A semiconductor device includes semiconductor channel members vertically stacked over a substrate, a gate stack wrapping around the semiconductor channel members, a gate spacer disposed on sidewalls of the gate stack, a source/drain (S/D) epitaxial feature in contact with the semiconductor channel members, and an insulating layer interposing the S/D epitaxial feature and the gate stack. The insulating layer, the S/D epitaxial feature, and the gate spacer collectively define air gaps stacked between adjacent ones of the semiconductor channel members.