Inner Spacer Structure for Nanosheet Gate Capacitance Isolation
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Solution Overview
Problem
The existing nanosheet transistors in 3D-stacked semiconductor devices face issues with inner spacers having a half-oval or semicircle shape, leading to increased capacitance, reduced AC performance, and potential damage to source/drain regions during etching, which affects production yield and device performance.
Innovation Solution
The implementation of thick inner spacers with rectangular or substantially rectangular shapes, where the top surface is higher than the inner gate structure and the bottom surface is lower, effectively isolating the gate structure from the source/drain regions, reducing proximity and preventing etchant penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inner spacers are formed with conventional half-oval or semicircle shapes, then the manufacturing process is simpler, but the capacitance increases and AC performance deteriorates
Solution Approach 1:
The patent transitions from conventional 2D planar inner spacer shapes (half-oval/semicircle) to a 3D rectangular prism structure that extends vertically between channel layers. This dimensional change enables the inner spacer to provide effective electrical isolation while maintaining compact footprint, thereby reducing capacitance without complicating the manufacturing process significantly.
Solution Approach 2:
The patent changes the geometric parameters of the inner spacer from curved 2D shapes to a rectangular 3D structure with specific dimensions (thickness greater than inner gate structure, top surface higher than inner gate structure, bottom surface lower than inner gate structure). These parameter changes optimize the electrical isolation performance and reduce capacitance while maintaining manufacturability.
2Reliability
If inner spacers are made thinner to reduce capacitance, then AC performance improves, but source/drain regions become vulnerable to etchant penetration and damage
Solution Approach 1:
The patent optimizes the thickness parameter of the inner spacer to be greater than that of the inner gate structure, creating a robust barrier that prevents etchant penetration while maintaining effective electrical isolation. This parameter optimization resolves the contradiction between reducing capacitance and protecting source/drain regions.
Solution Approach 2:
The thick inner spacer structure serves as a protective barrier formed beforehand to prevent etchant from reaching and damaging the source/drain regions during subsequent manufacturing processes. This proactive design protects vulnerable areas before harmful exposure can occur.
3Ease of manufacture
If inner spacers are formed at the same level as inner gate structures, then the manufacturing process is simpler, but electrical isolation between gate and source/drain is insufficient
Solution Approach 1:
The patent extends the inner spacer structure vertically in the third dimension, making it taller than the inner gate structure. This vertical extension creates effective electrical isolation between the gate and source/drain regions while maintaining a manufacturable structure through standard deposition and etching processes.
Solution Approach 2:
The inner spacer is designed with different local characteristics: the top surface extends higher than the inner gate structure to provide isolation from upper channel layers, while the bottom surface extends lower to isolate from lower channel layers. This localized quality differentiation optimizes electrical isolation at different positions.
Data Source
AI summary
Provided is a semiconductor device which includes: a plurality of 1st channel layers arranged in a 1st direction; a 1st source/drain region on the plurality of 1st channel layers; a 1st gate structure including a 1st inner gate structure between two adjacent 1st channel layers among the plurality of 1st channel layers; and a 1st inner spacer between the 1st inner gate structure and the 1st source/drain region, wherein a top surface of the 1st inner spacer is at a higher level than a top surface of the 1st inner gate structure, and a bottom surface of the 1st inner spacer is at a lower level than a bottom surface of the 1st inner gate structure, in the 1st direction.