Inner Spacer Dielectric Layers for Semiconductor Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the effective capacitance and improving the performance of semiconductor devices due to the limitations in forming inner spacers that effectively isolate gate stacks from source/drain regions, particularly in nanostructure field-effect transistors (NSFETs), where conventional materials and processes result in high dielectric constants and excessive etching issues.
Innovation Solution
The formation of inner spacers using multiple dielectric layers with different compositions, including a high etch selectivity first layer and low-k value second and third layers, such as silicon carbonitride and silicon oxycarbonitride, which reduce the effective capacitance and improve etch resistance and profiles, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used for inner spacers, then the isolation between gate stacks and source/drain regions is achieved, but the effective capacitance remains high and etching issues occur
Solution Approach 1:
The inner spacer is formed as a composite structure with a first dielectric layer (higher etch selectivity) and a second dielectric layer (lower dielectric constant). This composite approach allows the first layer to provide etch resistance during fabrication while the second layer reduces effective capacitance, simultaneously addressing both isolation reliability and harmful effects.
Solution Approach 2:
Different regions of the inner spacer are assigned different dielectric properties: the first dielectric layer (e.g., silicon carbonitride) provides high etch selectivity for fabrication processes, while the second dielectric layer (e.g., silicon oxycarbonitride) provides low dielectric constant for capacitance reduction. This local differentiation resolves the contradiction between isolation quality and capacitance control.
2Ease of manufacture
If single-layer dielectric spacers are formed, then the fabrication process is simple, but etch resistance is insufficient and profiles are poor
Solution Approach 1:
The inner spacer dielectric layer is segmented into two distinct layers with different compositions and functions. The first layer (silicon carbonitride) is optimized for etch resistance and profile control, while the second layer (silicon oxycarbonitride) is optimized for low capacitance. This segmentation improves manufacturing precision without significantly complicating the fabrication process.
Solution Approach 2:
The dielectric layers are deposited with controlled thickness parameters and compositional gradients. The first dielectric layer has higher nitrogen content for etch resistance, while the second layer has higher oxygen content for lower dielectric constant. By adjusting these compositional parameters, both etch resistance and profile quality are improved.
3Object-generated harmful factors
If dielectric layers with low dielectric constant are used, then effective capacitance is reduced, but etch resistance decreases
Solution Approach 1:
The solution uses a composite dielectric structure where the first layer (silicon carbonitride) provides high etch resistance with moderate dielectric constant, and the second layer (silicon oxycarbonitride) provides low dielectric constant with reduced etch resistance. The combination achieves overall low effective capacitance while maintaining sufficient etch resistance through the first layer.
Solution Approach 2:
Different dielectric layers are assigned different quality characteristics: the first layer has high nitrogen content for etch resistance, while the second layer has higher oxygen content for lower dielectric constant. This local quality differentiation allows the structure to simultaneously achieve low capacitance and adequate etch resistance.
Data Source
AI summary
Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.