Nanostructure Transistor Inner Spacer Etching for Uniform Thickness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of inner spacers in nanostructure transistors is challenging due to corner rounding during cavity formation, leading to reduced lateral thickness and increased risk of etching through the spacers, which can damage the source/drain regions and cause electrical shorting, resulting in transistor failure and reduced yield.
Innovation Solution
A multiple-etch process is employed to form cavities for inner spacers, involving one or more first etch operations followed by second etch operations to trim the corners, achieving sharper transitions and increased uniformity in lateral spacer thickness, thereby reducing the likelihood of etching through the spacers during the replacement gate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single etch operation is used to form cavities for inner spacers, then the process is simple and fast, but corner rounding occurs leading to reduced lateral thickness and increased risk of etching through the spacers
Solution Approach 1:
The etch process is segmented into multiple distinct operations: a first etch operation to form the cavity, followed by a second etch operation to trim the corners. This segmentation allows each operation to be optimized for its specific purpose, with the second operation specifically targeting corner rounding to improve lateral thickness uniformity without affecting the overall process simplicity excessively.
Solution Approach 2:
The first etch operation performs the preliminary action of forming the cavity with sufficient lateral thickness, and the second etch operation then performs the preliminary trimming action on the corners. This preliminary action sequence ensures that the inner spacers will have uniform lateral thickness before the replacement gate operation, preventing etching through the spacers.
2Reliability
If corner rounding is not trimmed, then the manufacturing process is simpler, but the lateral thickness of inner spacers is reduced leading to etching through and source/drain region damage
Solution Approach 1:
The manufacturing process is segmented into a first etch operation for cavity formation and a second etch operation for corner trimming. This segmentation enables the process to achieve high reliability by eliminating corner rounding that would otherwise cause reduced lateral thickness and potential etching through the spacers, while maintaining reasonable ease of manufacture through standardized etch procedures.
Solution Approach 2:
The corner rounding, which initially appears as a harmful defect reducing lateral thickness, is converted into a beneficial process feature by deliberately adding a second etch operation to trim these corners. This transforms the potential failure mode into a controlled process step that actually improves spacer uniformity and prevents etching through, thereby increasing transistor yield.
3Reliability
If inner spacers are formed with insufficient lateral thickness, then the cavity formation is easier, but the spacers are prone to etching through during replacement gate operation causing electrical shorting
Solution Approach 1:
The second etch operation performs a preliminary trimming action on the corners of the cavity before the inner spacers are fully formed or before the replacement gate operation. This preliminary corner removal ensures that the lateral thickness of the inner spacers is sufficient and uniform, preventing etching through during the replacement gate operation and maintaining electrical isolation between source and drain regions.
Solution Approach 2:
The multi-etch process incorporates implicit feedback by using the first etch operation to form the cavity and then using the second etch operation to correct any corner rounding that occurred. This feedback mechanism ensures that the final spacer geometry meets the required lateral thickness specifications for reliable electrical isolation, preventing the harmful effect of etching through the spacers.
Data Source
AI summary
A multiple-etch process is performed to form cavities in which inner spacers of a nanostructure transistor are to be formed. The multiple-etch process includes one or more first etch operations to form the cavities, and one or more second etch operations to trim the corners of the cavities to reduce corner rounding in the corners of the cavities. The corners of the cavities have greater orthogonality between the sidewalls and inner surface of the cavities as a result of the one or more second etch operations being performed. This results in increased uniformity in the lateral thickness of the inner spacers that are subsequently formed in the cavities. The increased uniformity in the lateral thickness of the inner spacers reduces the likelihood of etching through any particular part of the inner spacers during a replacement gate operation to replace sacrificial nanostructure layers with the gate structure of the nanostructure transistor.