Inner Spacer Structure for Selective GAA FET Sacrificial Etching
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in forming inner spacers for gate-all-around field effect transistors (GAA FETs) due to insufficient etching selectivity, which leads to unintended formation of inner spacers over the bottom sacrificial layer, blocking the formation of buried dielectric layers and degrading the reliability and performance of integrated circuits (ICs).
Innovation Solution
A method for forming inner spacers in GAA FETs involves epitaxially growing a bottom and top sacrificial layer with different germanium atomic concentrations. A radical etching process with a fluorine-containing etchant is used to selectively etch the top sacrificial layer over the bottom sacrificial layer, achieving an etching selectivity greater than 5, thereby allowing the formation of inner spacers only on the top sacrificial layer, exposing the bottom sacrificial layer for subsequent replacement with a buried dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form inner spacers, then inner spacers can be formed, but unintended inner spacers are also formed over the bottom sacrificial layer, blocking buried dielectric layer formation
Solution Approach 1:
The patent applies local quality by creating spatial differentiation in etching selectivity across different regions of the sacrificial layers. The top sacrificial layer is designed to be selectively etched by the fluorine-containing radical etchant, while the bottom sacrificial layer remains protected. This local differentiation in etching response allows inner spacers to form only where intended (over the top sacrificial layer) while preserving the bottom sacrificial layer for subsequent buried dielectric layer formation.
Solution Approach 2:
The patent employs parameter changes by modifying the etching process parameters, specifically using a fluorine-containing radical etchant with controlled conditions to achieve etching selectivity greater than 5 between the top and bottom sacrificial layers. This parameter optimization ensures that the etching process selectively removes the top sacrificial layer material while leaving the bottom sacrificial layer intact, thereby preventing unintended inner spacer formation.
2Manufacturing precision
If etching selectivity is insufficient, then inner spacers form over both sacrificial layers, but this blocks the formation of buried dielectric layers and degrades IC performance
Solution Approach 1:
The patent achieves the required etching selectivity greater than 5 by optimizing etching process parameters, including the use of fluorine-containing radical etchants and controlling etching conditions. This parameter optimization ensures high-selectivity etching that forms inner spacers only over the top sacrificial layer, thereby enabling subsequent buried dielectric layer patterning to proceed with high yield and preventing degradation of IC performance.
3Ease of manufacture
If inner spacers block the bottom sacrificial layer, then inner spacer formation is simplified, but the formation of buried dielectric layers is blocked
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially selective etching. The etching process is designed to affect only the top sacrificial layer locally, while the bottom sacrificial layer remains untouched. This localized approach allows inner spacers to form easily over the top sacrificial layer without blocking the bottom sacrificial layer, thereby maintaining simplicity in inner spacer formation while preserving the ability to form buried dielectric layers subsequently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of patterning the buried dielectric layer, improves the reliability and performance of GAA FETs, and ensures the correct formation of inner spacers, thereby addressing the challenges of etching selectivity and substrate leakage current in semiconductor manufacturing.
Implementation Method 1
A radical etching process with a fluorine-containing etchant is used to selectively etch the top sacrificial layer over the bottom sacrificial layer
Implementation Method 2
The radical etching process can apply a fluorine-containing radical, such as a F radical, to react with the top sacrificial layer with an activation energy less than reacting with the bottom sacrificial layer
Implementation Method 3
epitaxially growing a bottom and top sacrificial layer with different germanium atomic concentrations
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.