Inner Spacer Gap Under Multi-Gate Source/Drain for Lower Leakage
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Solution Overview
Problem
Multi-gate transistors, particularly multi-bridge-channel (MBC) transistors, face issues with limited gate control over the mesa due to the gate structure engaging only the top surface, leading to leakage paths and performance degradation from source/drain feature contact with the substrate, affecting resistive-capacitive (RC) delay and source-gate capacitance.
Innovation Solution
A method involving the formation of fin-shaped structures with interleaved sacrificial and channel layers, recessing these layers to create inner spacer recesses, depositing dielectric and polymer layers, and epitaxially growing source/drain features to minimize contact with the substrate, using selective etching and deposition processes to control the size and spacing of these features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain features are allowed to contact the mesa to simplify manufacturing, then ease of manufacture is improved, but leakage current increases due to created leakage paths
Solution Approach 1:
An inner spacer layer is introduced as an intermediary between the source/drain feature and the mesa. This spacer layer prevents direct contact and eliminates leakage paths while maintaining manufacturing simplicity through conformal deposition processes.
Solution Approach 2:
The solution moves from a 2D planar contact approach to a 3D vertical spacing approach by depositing the inner spacer layer that extends into the source/drain recess, creating vertical separation between the source/drain feature and mesa surfaces.
2Object-generated harmful factors
If source/drain features are spaced away from the substrate to reduce leakage, then leakage current is reduced, but device complexity increases due to additional processing steps
Solution Approach 1:
The inner spacer layer is formed through self-aligned conformal deposition processes where the spacer material automatically deposits on exposed surfaces including the mesa and sidewalls, eliminating the need for separate alignment and positioning steps that would increase complexity.
Solution Approach 2:
The inner spacer layer is deposited early in the fabrication sequence before source/drain feature formation, preliminarily establishing the leakage prevention structure that will guide subsequent processing steps and simplify later manufacturing operations.
3Reliability
If inner spacer layer is conformally deposited to ensure complete coverage, then reliability is improved by eliminating leakage paths, but manufacturing precision requirements increase due to controlled etching back
Solution Approach 1:
The conformal deposition process provides inherent feedback control where the spacer layer thickness is determined by deposition time and rate, ensuring uniform coverage. The subsequent selective etching uses the polymer layer as a thickness reference, automatically stopping when the polymer is exposed, which provides self-regulating precision control.
4Reliability
If polymer layer is used to protect dielectric layer during etching, then reliability is improved by preventing over-etching, but loss of substance occurs due to polymer removal
Solution Approach 1:
The polymer layer is used as a temporary, disposable protective element that is deliberately deposited, serves its protective function during critical etching steps, and is then completely removed. This short-living object approach is economically justified by the high reliability it provides during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces leakage current and maintains optimal RC delay by vertically spacing source/drain features from the substrate, allowing for controlled resistance and capacitance adjustments, thereby enhancing the performance of multi-gate transistors.
Implementation Method 1
conformally depositing a dielectric layer over the substrate and the inner spacer recesses
Implementation Method 2
depositing a polymer layer over the dielectric layer
Implementation Method 3
etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate
Implementation Method 4
epitaxially growing source/drain features to minimize contact with the substrate
Data Source
AI summary
Multi-gate transistor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a fin-shaped structure over a substrate and including channel layers interleaved by sacrificial layers, recessing the fin-shaped structure to form a source/drain recess, recessing the sidewalls of the sacrificial layers to form inner spacer recesses, depositing a dielectric layer over the substrate and the inner spacer recesses, depositing a polymer layer over the dielectric layer, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate, and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess. The source/drain feature and the inner spacer layer define a gap.