Inner Spacer High-κ Removal for Lower Parasitic Capacitance
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Solution Overview
Problem
As transistor dimensions shrink, parasitic capacitances between transistor regions become more problematic, affecting performance and scalability.
Innovation Solution
A semiconductor IC device with a replacement gate structure that includes a high-κ layer directly connected to a nanolayer channel and a work function gate, and an inner spacer that is coplanar with the nanolayer channel, reducing the horizontal dimension of dielectric material between the source/drain region and the work function gate to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the transistor dimensions are reduced to increase device density, then device density improves, but parasitic capacitance between transistor regions increases
Solution Approach 1:
The patent removes the high-κ dielectric material from the inner spacer structure, extracting only the necessary portions to minimize parasitic capacitance while maintaining the beneficial high-κ layer in other critical areas for gate control
Solution Approach 2:
The patent applies different dielectric material properties to different spatial locations: high-κ material is retained in the gate stack for excellent gate control, while the inner spacer region uses reduced or removed high-κ material to minimize parasitic capacitance, creating locally optimized properties
2Object-generated harmful factors
If the horizontal dimension of dielectric material between source/drain and work function gate is reduced to minimize parasitic capacitance, then parasitic capacitance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary planarization and positioning of the inner spacer before final gate formation, ensuring the inner spacer is coplanar with the nanolayer channel surface in advance, which simplifies subsequent processing steps and maintains precision
Solution Approach 2:
The patent uses the inner spacer as an intermediary structure that defines the precise horizontal boundary between the source/drain region and the work function gate, with its coplanar top surface serving as a reference plane for maintaining manufacturing precision
Data Source
AI summary
A semiconductor integrated circuit (IC) device includes a first source/drain region connected to a second source/drain region by a plurality of active channels, a backside contact that is directly coupled to the first source/drain region, a frontside contact that is directly coupled to the second source/drain region, and a backside dielectric plug that is directly coupled to the second source/drain region and that is directly coupled to the backside contact. In examples, every backside contact placeholder that is associated with a source/drain region that is connected to a frontside contact is removed and replaced by a respective backside dielectric plug. Relative to the backside contact placeholder, the replacement backside dielectric plug may reduce gate-drain Miller capacitance, source/drain capacitance, and may reduce leakage current between source and drain through substrate residue that may reside due to flawed substrate removal during backside processing.