Inner Spacer Liner Structure for Preserving NMOS Mobility
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Solution Overview
Problem
In advanced semiconductor technology nodes, dimension scaling poses challenges in forming isolated contacts to semiconductor devices, particularly due to undesirable impurities being driven into and aggregating at interfaces between silicon nanosheets and SiGe during inner spacer formation, which reduces NMOS mobility in nanosheet transistor devices.
Innovation Solution
A silicon liner is selectively grown on silicon nanosheets and SiGe surfaces after source/drain region SiGe recessing, positioned between the high-k dielectric layer and inner spacers, to block impurities and prevent their drive-in and aggregation, thereby improving NMOS mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If inner spacers are formed during dimension scaling, then device integration density is improved, but impurities are driven into and aggregate at interfaces between silicon nanosheets and SiGe, reducing NMOS mobility
Solution Approach 1:
A silicon-germanium (SiGe) liner layer is introduced as an intermediary barrier between the inner spacer and the silicon nanosheet/SiGe interface. This liner layer selectively blocks impurity diffusion into the channel region while permitting beneficial stressors to reach the interface, thereby resolving the contradiction between maintaining high device integration density and preserving NMOS mobility
Solution Approach 2:
The SiGe liner layer is selectively positioned only at critical interfaces where impurity aggregation occurs, providing localized protection without affecting the overall device structure. This targeted approach maintains high integration density while locally preventing mobility degradation at the silicon nanosheet/SiGe interface
2Ease of manufacture
If traditional dielectric materials are used in inner spacers, then manufacturing simplicity is maintained, but impurity blocking effectiveness is insufficient
Solution Approach 1:
The inner spacer structure is transformed from a simple dielectric material into a composite structure comprising a SiGe liner layer combined with dielectric material. This composite approach provides superior impurity blocking performance while maintaining compatibility with existing manufacturing processes, thus resolving the contradiction between manufacturing simplicity and impurity blocking effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The silicon liner effectively prevents the drive-in and aggregation of impurities at the interfaces, enhancing the mobility of NMOS devices by acting as a better barrier than traditional dielectric materials used in inner spacers.
Implementation Method 1
A silicon liner is selectively grown on silicon nanosheets and SiGe surfaces after source/drain region SiGe recessing, positioned between the high-k dielectric layer and inner spacers, to block impurities and prevent their drive-in and aggregation
Data Source
AI summary
A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.