Multi-Layer Inner Spacer Structure for Low-Capacitance Semiconductors
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing effective capacitance and improving performance due to limitations in the design and materials used for inner spacers, which affect the integration density and reliability of electronic components.
Innovation Solution
The formation of inner spacers using multiple dielectric layers with different compositions, including a high etch selectivity first layer and low-k value second and third layers, such as silicon carbonitride and silicon oxycarbonitride, to enhance etch resistance and reduce effective capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single-layer inner spacers are used, then manufacturing process is simple, but effective capacitance cannot be reduced and etch resistance is insufficient
Solution Approach 1:
The inner spacer is divided into multiple layers (first inner spacer layer with high etch selectivity, second inner spacer layer with low-k value, and third inner spacer layer) instead of using a single uniform layer. This segmentation allows each layer to perform its specific function: the first layer provides etch resistance, the second layer reduces capacitance, and the third layer provides additional protection, thereby resolving the contradiction between etch resistance and structural complexity.
Solution Approach 2:
The inner spacer structure uses composite materials with different properties arranged in layers. The first inner spacer layer uses materials with high etch selectivity (such as silicon nitride or silicon carbonitride), while the second inner spacer layer uses low-k dielectric materials. This composite structure combines the advantages of different materials to achieve both etch resistance and capacitance reduction simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the profiles and reduces the effective capacitance of semiconductor devices, leading to enhanced performance and reduced device defects, while maintaining etch resistance and minimizing excessive etching.
Implementation Method 1
the first inner spacer layer having a first etch selectivity with respect to a etch process used to remove the first semiconductor layers, a second etch selectivity with respect to a etch process used to pattern the second inner spacer layer, and a third etch selectivity with respect to a etch process used to remove the third inner spacer layer
Implementation Method 2
the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer
Data Source
AI summary
Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.