Inner Spacer Profile in Nanosheet Gates for Stable Electrical Characteristics
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Solution Overview
Problem
The increasing demands for high performance, speed, and multifunctionality in semiconductor devices require finer patterns and three-dimensional structures like FinFETs and nanosheet transistors, but existing technologies face challenges in achieving improved integration and reliability due to size reduction limitations.
Innovation Solution
A semiconductor device design featuring a gate structure with varying inner spacers having increasing heights and decreasing thicknesses towards the bottom, along with channel layers and source/drain regions, to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar MOSFET structures are used, then manufacturing is simpler, but size reduction limitations and operating characteristics deteriorate
Solution Approach 1:
The patent transitions from conventional planar (2D) MOSFET structures to three-dimensional FinFET structures with channels extending in the vertical direction. This dimensional change enables continued scaling and improved operating characteristics by utilizing the third dimension for current flow, thereby overcoming the size reduction limitations of planar devices.
Solution Approach 2:
The channel region is segmented into multiple fins extending vertically, creating multiple parallel current paths. This segmentation allows the device to maintain effective channel width while reducing the planar footprint, thereby improving integration density without sacrificing operating characteristics.
2Reliability
If inner spacers have uniform dimensions, then manufacturing is easier, but gate structure stability and electrical characteristics deteriorate
Solution Approach 1:
The inner spacers are designed with non-uniform dimensions where the thickness varies along the vertical direction. Specifically, the inner spacers have greater thickness at upper levels and reduced thickness at lower levels. This local variation in dimensions allows optimization of gate structure stability and electrical characteristics at different vertical positions, addressing the contradiction between uniform manufacturing and performance requirements.
3Productivity
If channel layers are closely spaced, then integration density improves, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple channel layers in the third direction, spaced apart at intervals. This vertical stacking approach enables high integration density without requiring extremely close horizontal spacing, thereby maintaining manufacturing precision while achieving high productivity through three-dimensional device architecture.
Data Source
AI summary
A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.