Inner Spacer Formation for Precise Etching in GAA Semiconductors
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes due to the scaling-down of feature sizes, which complicates the formation of intricate semiconductor structures.
Innovation Solution
A method involving the use of double-patterning or multi-patterning processes to create semiconductor structures, including the formation of fins and gate all around (GAA) transistors, with the incorporation of inner spacers and epitaxial structures to enhance etching selectivity and oxidation rates, and the use of modifying treatments to increase the etching resistance of semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and reliability decreases
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned double patterning) where each step creates a portion of the final pattern. This segmentation allows complex structures to be built through simpler, repeatable steps, managing overall process complexity while achieving high functional density
Solution Approach 2:
Mandrel structures and spacer layers are formed in advance before the final pattern transfer. These preliminary structures serve as templates that guide subsequent etching steps, enabling precise feature formation without requiring direct patterning of the final geometry
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The self-aligned spacer formation process uses the mandrel structure itself to define the position of the final feature. The spacer width is controlled by conformal deposition thickness rather than lithographic patterning, providing superior dimensional control and precision at scaled dimensions
Solution Approach 2:
The patent controls feature dimensions by adjusting deposition parameters (film thickness, conformality) and etch parameters (selectivity, anisotropy) rather than relying solely on lithographic resolution. This parameter control enables precise feature sizing even as feature dimensions decrease
3Manufacturing precision
If inner spacers and epitaxial structures are incorporated to enhance etching selectivity, then etching precision is improved, but device structure complexity increases
Solution Approach 1:
Inner spacers serve as intermediary structures that protect certain regions during etching while allowing access to other regions. These spacers are selectively removed after serving their protective function, enabling precise control over etch depth and pattern formation without requiring complex masking schemes
Solution Approach 2:
The patent employs composite structures combining different materials (e.g., silicon nitride spacers, silicon oxide mandrels, semiconductor layers) with distinct etch selectivities. This material diversity enables differential etching of various structure components, achieving high etching precision through material properties rather than geometric complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of semiconductor devices with improved etching precision and reduced fabrication complexity, leading to enhanced device performance and reliability at smaller scales.
Implementation Method 1
introducing modifying elements into the sacrificial layers and the semiconductor layers to transform surface portions of the sacrificial layers and the semiconductor layers into a modified layer
Implementation Method 2
the formation of fins and gate all around (GAA) transistors, with the incorporation of inner spacers and epitaxial structures to enhance etching selectivity
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the semiconductor layers and the sacrificial layers to expose side edges of the semiconductor layers and the sacrificial layers and partially removing the sacrificial layers from their side edges to form multiple second recesses. The method further includes introducing modifying elements to transform surface portions of the sacrificial layers and the semiconductor layers into a modified layer. The modifying elements includes nitrogen, carbon, boron, or a combination thereof. In addition, the method includes forming an inner spacer layer over the modified layer and removing the inner spacer layer and the modified layer outside of the second recesses. Remaining portions of the inner spacer layer and the modified layer form inner spacers and modified elements, respectively.