Inner Spacer Structure for Selective GAA Sacrificial Layer Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in forming inner spacers for gate-all-around field effect transistors (GAA FETs) due to insufficient etching selectivity between top and bottom sacrificial layers, which can lead to unreliable and low-performing integrated circuits (ICs) as the inner spacers may unintentionally cover the bottom sacrificial layer, blocking the formation of a buried dielectric layer and degrading IC reliability and performance.
Innovation Solution
The method involves epitaxially growing a top sacrificial layer with a higher germanium atomic concentration than the bottom sacrificial layer, forming a recess structure to expose their side surfaces, and using a radical etching process with fluorine-containing etchants to selectively etch the top sacrificial layer, ensuring an etching selectivity greater than 5:1, thereby forming inner spacers only on the top layer and allowing the bottom layer to be exposed for subsequent replacement with a buried dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used, then the manufacturing process is simple, but the etching selectivity between top and bottom sacrificial layers is insufficient, causing inner spacers to unintentionally cover the bottom sacrificial layer
Solution Approach 1:
The patent applies local quality by creating distinct germanium concentration zones within the sacrificial layers. The top sacrificial layer has a higher germanium atomic concentration than the bottom sacrificial layer, which creates different etching rates in different regions. This local compositional variation enables selective etching of the top layer while preserving the bottom layer, directly resolving the etching selectivity issue.
Solution Approach 2:
The patent changes the chemical composition parameter (germanium atomic concentration) of the sacrificial layers to achieve different etching characteristics. By controlling the germanium content during epitaxial growth, the top sacrificial layer becomes more susceptible to fluorine-containing radical etchants than the bottom layer, achieving the required etching selectivity greater than 5:1.
2Reliability
If inner spacers cover the bottom sacrificial layer, then the manufacturing process is simpler, but the buried dielectric layer formation is blocked, degrading IC reliability and performance
Solution Approach 1:
The patent performs preliminary action by forming the recess structure and selectively etching the top sacrificial layer before the inner spacer formation step. This preliminary etching creates exposed sidewalls of the bottom sacrificial layer, ensuring that subsequent inner spacer deposition occurs only on the top layer. This prevents the spacer from covering the bottom sacrificial layer and blocking buried dielectric layer formation, thereby ensuring both reliability and productivity.
3Manufacturing precision
If higher germanium concentration is used in top sacrificial layer, then etching selectivity is improved, but the material composition control becomes more difficult
Solution Approach 1:
The patent systematically changes the germanium atomic concentration parameter during the epitaxial growth process. By controlling the germanium precursor flow rates and temperature profiles during different growth stages, the top sacrificial layer is grown with higher germanium content than the bottom layer. This parameter control approach achieves the required etching selectivity while maintaining manufacturing feasibility through established epitaxial growth techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of patterning the buried dielectric layer, improving the reliability and performance of GAA FETs by ensuring precise formation of inner spacers and preventing substrate leakage current, thus boosting the overall performance of integrated circuits.
Implementation Method 1
using a radical etching process with fluorine-containing etchants to selectively etch the top sacrificial layer
Implementation Method 2
fluorine-containing etchants to selectively etch the top sacrificial layer
Implementation Method 3
epitaxially growing a top sacrificial layer with a higher germanium atomic concentration than the bottom sacrificial layer
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.