Inner Spacer Material Selection for Threshold Voltage Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tuning the threshold voltage of fully depleted semiconductor devices, such as fin field effect transistors and nanosheet field effect transistors, is challenging due to the difficulty in patterning work function materials in the limited space between nanosheets, which can lead to pinch-off issues.
Innovation Solution
The method involves forming first and second inner spacer sub-layers from different dielectric materials within recesses of a stack of alternating sacrificial and channel layers, allowing for the replacement of sacrificial layers and the formation of a gate stack in contact with the second inner spacer sub-layer, enabling control over threshold voltage by filling oxygen vacancies in the gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional patterning methods are used to adjust threshold voltage by depositing work function materials, then threshold voltage tuning is achieved, but the limited space between nanosheets causes pinch-off that is difficult to remove
Solution Approach 1:
The gate dielectric layer is segmented into multiple regions with different thicknesses by forming recesses at specific locations. This segmentation allows different work function materials to be deposited on different regions, enabling threshold voltage tuning without requiring complex patterning in the confined nanosheet space. The recesses create distinct zones where material deposition can occur independently.
Solution Approach 2:
Instead of attempting to pattern materials horizontally in the limited space between nanosheets, the invention transitions to vertical dimensionality by forming recesses of varying depths in the gate dielectric. This vertical approach allows multiple material regions to be created without lateral patterning, avoiding the pinch-off problem while achieving the same threshold voltage tuning function.
2Reliability
If different work function materials are used to select different electrical properties, then device performance is improved, but additional patterning steps are required that are challenging for nanosheet devices
Solution Approach 1:
The gate dielectric recesses are formed in advance before work function material deposition. This preliminary structuring of the gate dielectric with pre-defined regions of different depths allows subsequent material deposition to automatically create the desired electrical properties without requiring additional patterning steps. The preliminary action eliminates the need for complex post-deposition patterning.
Solution Approach 2:
Different regions of the gate dielectric are given different local qualities through varying recess depths, allowing specific areas to interact differently with deposited work function materials. This local differentiation enables precise control of electrical properties in different device regions while using a single unified deposition process, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively tunes the threshold voltage of semiconductor devices by using high-k gate dielectric materials in contact with inner spacers of varying materials, improving device performance and overcoming the limitations of traditional patterning methods.
Implementation Method 1
enabling control over threshold voltage by filling oxygen vacancies in the gate dielectric
Data Source
AI summary
Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.