Inner Spacer Structure With Variable Ge for Nanosheet Isolation
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Solution Overview
Problem
Conventional nano-sheet-based transistors face challenges in maintaining feature integrity and reliability due to poor electronic isolation between source/drain features and gate structures, which is exacerbated by the scaling down process, leading to potential damage and performance degradation.
Innovation Solution
The development of nano-sheet-based devices with inner spacer structures having less rounded sidewall surfaces, featuring a more square-like profile to maintain lateral width and facilitate scale-down while reducing curvature, thereby enhancing protection and isolation between source/drain features and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If inner spacer structures with less rounded sidewall surfaces are formed to maintain lateral width, then feature integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The sidewall profile of inner spacer structures is controlled by adjusting deposition parameters and etching conditions. By modifying process parameters such as deposition temperature, pressure, and etch chemistry, the sidewalls are formed with reduced curvature and maintained lateral width, achieving better feature integrity through parameter optimization rather than complex structural designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance and reliability of nano-sheet-based transistors by maintaining feature integrity and reducing damage during processing, while allowing for further scaling without compromising device density.
Implementation Method 1
A first portion of the second layer is laterally and selectively etched to form an opening between an end portion of the first layer and an end portion of the third layer
Data Source
AI summary
A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.