Nanostructure Transistor Inner Spacer Geometry to Reduce Voids
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Solution Overview
Problem
Nanostructure transistors face fabrication challenges that lead to defects and voids in inner spacers and gate structures, reducing the yield and increasing manufacturing costs.
Innovation Solution
The formation of sacrificial nanosheets with specific geometric and dimensional properties, including concave-regions facing the source/drain region, to reduce defects and voids in inner spacers and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for nanostructure transistors, then manufacturing process can be simplified, but defects and voids form in inner spacers and gate structures reducing yield
Solution Approach 1:
The patent applies preliminary action by forming sacrificial nanosheets with specific geometric and dimensional properties before forming the inner spacers. The sacrificial nanosheets are prepared in advance with concave regions that will define the inner spacer geometry, ensuring proper formation before the actual spacer creation process occurs. This preliminary preparation of the sacrificial structure prevents defects and voids in the inner spacers.
Solution Approach 2:
The patent changes physical parameters of the sacrificial nanosheets, specifically their geometric and dimensional properties. The nanosheets are formed with specific thicknesses, widths, and concave region geometries that directly influence the inner spacer formation. By controlling these parameters of the sacrificial structure, the patent achieves defect-free inner spacers and gate structures.
2Productivity
If yield is increased through improved fabrication methods, then manufacturing costs decrease, but process complexity increases
Solution Approach 1:
The patent applies self-service through self-aligned formation processes where the sacrificial nanosheets automatically define the positions and geometries of the inner spacers and gate structures. The concave regions of the sacrificial nanosheets serve as templates that guide the subsequent material deposition and patterning steps, eliminating the need for separate alignment operations and reducing process complexity while maintaining high yield.
Solution Approach 2:
The patent employs nesting by having the inner spacers and gate structures formed within and around the sacrificial nanosheets. The sacrificial nanosheets contain the concave regions that will become the inner spacers, and these structures are nested within the overall transistor architecture. This nested approach allows multiple structures to be formed in a sequence that simplifies the overall fabrication process while achieving high precision.
Data Source
AI summary
Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.