InP Field-Effect Transistor Etch-Stop Structure for Low Access Resistance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing methods for producing InP-based field effect transistors face challenges in reducing access resistance between source/drain electrodes and the channel layer while maintaining electron mobility and preventing the short channel effect, due to difficulties in etching precision and surface flatness.

Innovation Solution

The method involves epitaxially growing a buffer layer, an etching stop layer of InxAl1-xP, and a channel layer of InyGa1-yAs, followed by patterning and regrowing contact layers, with an etching stop layer to reduce access resistance and enhance electron confinement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If spacer and barrier layers are removed, then access resistance is reduced, but electron confinement deteriorates

Engineering Contradiction:

Improveaccess resistanceVSAvoidelectron confinement

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The InP etching stop layer acts as an intermediary that enables selective removal of the InAlAs barrier layer while preserving the InGaAs channel layer. This selective etching reduces access resistance by removing the barrier layer but maintains electron confinement by preserving the channel layer integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces access resistance and suppresses the short channel effect, maintaining high electron mobility by using an InxAl1-xP etching stop layer with InyGa1-yAs channel layer, ensuring a flat surface for high-quality contact layer formation.

Implementation Method 1

an InP layer having a high etching selectivity with respect to InGaAs or InAlAs is inserted as an etching stop layer

Methodology Applied

Scientific EffectEtching selectivity:

Implementation Method 2

a first step of epitaxially growing a buffer layer comprising a compound semiconductor lattice-matched to InP

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

epitaxial crystal growth method such as molecular beam epitaxy (MBE)

Methodology Applied

Scientific EffectMolecular beam epitaxy:

Implementation Method 4

metal-organic vapor phase epitaxy (MOVPE)

Methodology Applied

Scientific EffectMetal-organic vapor phase epitaxy: Chemical Vapour Deposition

Data Source

PatentUS11824110B2Field effect transistor and method for manufacturing same

Publication Date: 2023.11.21 NIPPON TELEGRAPH & TELEPHONE CORP

AI summary

A buffer layer, an etching stop layer, and a channel layer are epitaxially grown in this order on a substrate. The substrate contains InP that has a high resistance by, for example, being doped with Fe. The buffer layer contains a compound semiconductor lattice-matched to InP. The etching stop layer includes InxAl1-xP (0≤x≤0.75). The channel layer contains InyGa1-y As (0<y≤1).