InP Layer Thinning via Phosphorus-Rich Conversion
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Solution Overview
Problem
Existing methods for thinning down InP layers on InGaAs fin structures in Fin-FETs introduce contaminants and complicate the fabrication process, leading to longer processing times and increased contamination risks due to the use of wet etching processes.
Innovation Solution
A method involving the conversion of a surface portion of the InP layer into a Phosphorus-rich layer followed by its removal using dry etching processes, specifically chemical dry etching with Cl2 and Ar for formation and HBr for removal, to achieve a thickness of the InP layer less than or equal to 1 nm, thereby avoiding contaminants and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching process is used to thin down the InP layer, then the InP layer can be removed, but contaminants are introduced and the fabrication process becomes more complicated
Solution Approach 1:
The patent changes the chemical composition parameters of the etching solution by incorporating specific organic chemicals (such as acetic acid, isopropyl alcohol, or ammonia) into the etching bath. This modification allows the solution to selectively etch the InP layer while minimizing contamination and enabling precise thickness control, thereby resolving the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The patent extracts and removes harmful contaminants from the etching process by using a specially formulated etching solution that selectively removes only the desired InP material without introducing unwanted impurities. The solution is designed to leave the underlying InGaAs layer intact while achieving the required thinning, thus simplifying subsequent processing steps
2Manufacturing precision
If wet etching process is used to thin down the InP layer, then the InP layer can be removed, but processing time increases
Solution Approach 1:
The patent optimizes the etching kinetics by adjusting parameters such as solution composition, temperature, and agitation rate. The modified etching solution achieves faster etching rates with better selectivity, reducing the overall processing time while maintaining precise thickness control through controlled etching conditions
Solution Approach 2:
The patent employs a multi-step etching approach where the InP layer is removed in controlled stages, allowing for intermediate inspections and adjustments. This partial action approach ensures precise thickness control while optimizing total processing time by avoiding over-etching and rework
3Manufacturing precision
If wet etching process is used to thin down the InP layer, then the InP layer can be removed, but the probability of device contamination increases
Solution Approach 1:
The patent changes the chemical parameters of the etching environment by using a closed-loop liquid etching system with controlled atmosphere, temperature, and solution flow rates. These parameter controls prevent external contamination while maintaining effective InP layer removal, thus improving device reliability without sacrificing manufacturing precision
Solution Approach 2:
The patent implements an inert atmosphere environment during the wet etching process by conducting the etching in a controlled chamber filled with inert gas (such as nitrogen or argon). This inert environment prevents oxidation and contamination of the InP layer and underlying structures, significantly reducing device contamination risk while maintaining precise thickness control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise thinning of the InP layer with reduced surface damage and contamination risks, enhancing the performance and reliability of Fin-FETs by minimizing exposure to dry and wet operation environments and shortening processing times.
Implementation Method 1
converting a surface portion of the InP layer into a Phosphorus-rich layer
Implementation Method 2
removing the Phosphorus-rich layer... using dry etching processes, specifically chemical dry etching with Cl2 and Ar for formation and HBr for removal
Data Source
AI summary
The disclosed subject matter provides a Fin-FET with a thinned-down InP layer and thinning-down method thereof. In a Fin-FET, the fin structure is made of InGaAs and an InP layer is formed to cover the fin structure. The InP layer is obtained from an initial InP layer formed on the fin structure through a thinning down process including converting a surface portion of the InP layer into a Phosphorus-rich layer and removing the Phosphorus-rich layer. The thickness of the ultimately-formed InP layer is less than or equal to 1 nm. According to the disclosed method, the InP layer in the Fin-FET may be easily thinned down, and during the thinning-down process, contamination may be avoided.