In-Place Code Integrity Check via External Memory Partitioning
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Solution Overview
Problem
The high cost and latency issues associated with verifying program code integrity in safety-critical systems, particularly due to the need for large amounts of internal SRAM to store error detection codes for entire program codes, which is costly and introduces runtime latency.
Innovation Solution
Implementing a system with integrity check circuitry that uses a two-partition scheme in external memory to verify program code integrity on a per-word basis, utilizing comparator and repair circuitry to ensure data integrity without requiring extensive internal SRAM, by comparing data from two non-overlapping partitions and generating an alarm signal for corrupted data, thereby minimizing latency and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection codes are stored in internal SRAM for entire program code verification, then code integrity verification capability is improved, but on-chip memory cost and runtime latency increase
Solution Approach 1:
The external memory is divided into two non-overlapping partitions: a first partition storing the program code and a second partition storing error detection codes. This segmentation allows verification without requiring large internal SRAM buffers, as data is verified directly from external memory partitions.
Solution Approach 2:
A dedicated integrity check circuit is introduced as an intermediary component between the external memory and the processor. This circuit performs verification of program code and error detection codes using comparator circuitry, eliminating the need for extensive internal SRAM while maintaining verification capability.
2Reliability
If error detection codes are stored in internal SRAM for entire program code, then verification capability is improved, but runtime latency increases
Solution Approach 1:
Error detection codes are pre-computed and stored in the second partition of external memory alongside the program code. This preliminary preparation allows for rapid verification during runtime without requiring complex computations or large internal buffers, thus minimizing latency.
Solution Approach 2:
The patent replaces the traditional mechanical approach of copying entire program codes into internal SRAM for verification with an electronic/direct access approach. The integrity check circuit directly accesses external memory partitions and performs verification using comparator circuitry, eliminating the time-consuming copy operation and reducing runtime latency.
3Adaptability or versatility
If deep sub-micron technologies are used for fabrication, then integration capability is improved, but cost of embedded non-volatile memory increases
Solution Approach 1:
The patent extracts the error detection and verification functionality from the internal SRAM architecture and relocates it to external memory partitions. By storing program code and error detection codes in external memory partitions rather than internal SRAM, the system reduces dependence on expensive on-chip memory while maintaining verification capability through the integrity check circuit.
Data Source
AI summary
Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.