Input Bias Control Using Clock Detection for FSM Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Synchronizing multiple asynchronous finite state machines in systems is complex due to differing operation times, leading to potential loss of synchronization and system malfunctions, which can result in catastrophic failures.
Innovation Solution
A clock detect circuit generates a signal for an operational state detect circuit, which enables pull-up or pull-down transistors to manage input buffers based on the operational state of the module, ensuring synchronized operation by enabling transistors at predetermined times following external clock signal detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple asynchronous finite state machines are used to perform operations at different speeds, then system functionality and processing capability are improved, but synchronization complexity increases and system reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by enabling the input buffer before the finite state machine operates on the input data. This ensures that data is ready and stable before processing begins, preventing synchronization issues. The buffer is activated in advance based on clock signal detection, so when the finite state machine needs the data, it is already prepared and won't cause timing conflicts.
Solution Approach 2:
The patent implements dynamics by making the input buffer's enable state dynamic rather than static. The buffer transitions between enabled and disabled states based on the operational state of the finite state machine and clock signal detection. This dynamic control allows the system to adapt to different operational modes (asynchronous vs. synchronous) and maintain synchronization reliability while preserving processing capability.
2Reliability
If input buffering is enabled too early, then data readiness is improved, but power consumption increases due to unnecessary buffering operation
Solution Approach 1:
The system performs preliminary detection of clock signals to determine when buffering should be enabled, rather than enabling it continuously. This preliminary action allows the system to prepare buffers only when needed, ensuring data readiness while avoiding unnecessary power consumption during periods when buffering is not required.
Solution Approach 2:
The input buffer's operational state is made dynamic, transitioning between enabled and disabled based on real-time detection of clock signals and finite state machine status. This dynamic control ensures the buffer consumes power only when actually needed for data preparation, balancing data readiness with power efficiency.
3Measurement precision
If clock signal detection is used to control buffering, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using the existing clock signal, which already exists in the system for synchronizing finite state machines, to also control the input buffer enablement. This multi-functional use of the clock signal achieves precise synchronization without adding dedicated control circuits, thereby maintaining synchronization accuracy while avoiding increased device complexity.
Data Source
AI summary
This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the module. The operational state detect circuit enables one of a pull-up and pull-down transistor corresponding said operational state of the module. The operational state detect circuit may the input buffer a predetermined time following external clock signal detection, which might be a following transition in the external clock signal. The operational state detect circuit enables the pull-up or pull-down transistor a predetermined time following enabling said input buffer.