Input Buffer Bias Control for Stable Output Timing Under VDD Variation
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Solution Overview
Problem
Buffer circuits in semiconductor apparatuses are sensitive to variations in power supply voltage, leading to unstable output timing and duty of the output signal.
Innovation Solution
A buffer circuit design that includes a power supply voltage detection block, a bias generation block to produce constant and enable bias signals, and an input buffer enabled by these signals, which minimizes the impact of power supply voltage variations by forming current paths using a current mirror with first and second enable units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the buffer circuit uses the power supply voltage VDD as the bias voltage BIAS, then the buffer circuit can operate with a simple power supply connection, but the output timing and duty of the output signal become unstable due to variation in the power supply voltage level
Solution Approach 1:
The bias voltage generation is segmented into multiple independent bias voltages (first bias voltage and second bias voltage) with different characteristics. The first bias voltage has a level insensitive to power supply variations, while the second bias voltage level varies with power supply voltage. This segmentation allows the buffer circuit to maintain stable output timing and duty by using the stable first bias voltage for critical timing functions.
Solution Approach 2:
The invention changes the parameter characteristics of bias voltages by generating multiple bias voltages with different sensitivity levels to power supply variations. The first bias voltage is designed to have minimal variation with power supply changes, while the second bias voltage maintains correlation with power supply voltage. This parameter differentiation resolves the contradiction by providing both simplicity and stability.
2Reliability
If the buffer circuit uses a constant bias signal for stable operation, then the output signal stability improves, but additional bias generation circuits are required which increase device complexity
Solution Approach 1:
The power supply voltage detection block serves multiple functions: it detects the power supply voltage level, generates the first stable bias voltage, generates the second bias voltage correlated with power supply, and produces enable signals for selective bias application. This multi-functionality reduces overall device complexity while maintaining output signal stability.
Solution Approach 2:
The bias generation block uses the power supply voltage detection capability to automatically generate appropriate bias voltages without requiring external intervention. The system self-adjusts by detecting power supply conditions and generating the necessary first and second bias voltages with appropriate characteristics, reducing the need for additional external bias generation circuits.
Data Source
AI summary
A buffer circuit includes a power supply voltage detection block which may detect a voltage level of a power supply voltage, a bias generation block which may generate a constant bias signal and a plurality of enable bias signals based on the detection result of the power supply voltage, and an input buffer which may amplify an input signal in response to the constant bias signal and the plurality of enable bias signals.