Input Buffer With Common Gate Amplifier For Wide Common Mode Range
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Solution Overview
Problem
Existing input buffers for differential signals, such as those used in LVDS systems, face challenges with impedance mismatch, limited common mode voltage range, and poor common mode rejection ratio, especially when dealing with signals exceeding the supply voltage, leading to noise introduction during amplification.
Innovation Solution
An input buffer design incorporating a common gate amplifier with a bias circuit that generates a bias voltage higher than the supply voltage, allowing direct amplification and level shifting of incoming common mode voltages beyond the supply voltage, along with additional circuitry for feedback control and hysteresis reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a transimpedance amplifier is used as a level shifter to handle wide common mode input range, then the common mode input range is improved, but impedance mismatch occurs resulting in large offsets and poor common mode rejection ratio
Solution Approach 1:
The input buffer is divided into multiple stages: a first stage that performs level shifting and a second stage that provides amplification. This segmentation allows each stage to be optimized for its specific function, with the first stage handling wide common mode range and the second stage providing precise amplification with good CMRR.
Solution Approach 2:
A differential pair circuit is introduced as an intermediary between the level shifter and the amplification stage. This differential pair acts as a buffer that converts the single-ended output of the level shifter to differential signals, improving impedance matching and reducing offsets before further amplification.
2Adaptability or versatility
If level shifting is performed before amplification to handle signals exceeding supply voltage, then the input common mode voltage range is improved, but a DC offset is introduced that manifests as noise during subsequent amplification
Solution Approach 1:
The level shifting is performed in a dedicated first stage before the signal enters the amplification stages. By completing the level shifting operation beforehand, the subsequent amplification stages only need to amplify the already-shifted signal, preventing the amplification of DC offsets that would otherwise manifest as noise.
Solution Approach 2:
The level shifting function is extracted and separated from the amplification function into a distinct first stage. This separation allows the level shifter to handle voltage range conversion independently, while the amplification stages focus solely on signal gain, thereby avoiding the introduction and amplification of DC offsets.
3Measurement precision
If a folded cascode amplifier is used to improve level shifter mismatch, then the mismatch is reduced, but input common mode voltage is limited on both high and low sides and bandwidth is reduced making it unsuitable for high speed applications
Solution Approach 1:
The buffer is segmented into a first stage for level shifting and a second stage for high-speed amplification. This allows the first stage to focus on mismatch reduction while the second stage is optimized for bandwidth, achieving both low mismatch and high speed performance.
Solution Approach 2:
Different circuit topologies and parameter optimizations are applied to different stages: the first stage uses parameters optimized for low mismatch and wide common mode range, while the second stage uses parameters optimized for high bandwidth and gain, achieving overall high-speed performance with reduced mismatch.
Data Source
AI summary
In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.