Input Buffer Data Feedback Equalization Circuit for DRAM
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Solution Overview
Problem
Existing semiconductor memory devices, particularly DRAM, face challenges in ensuring accurate data latching across a wide range of inter-device variations due to factors like process, voltage, and temperature (PVT) variations.
Innovation Solution
The implementation of input buffer data feedback equalization (DFE) circuits, which include parallel DFE legs coupled in parallel between a capacitor and a node of the input buffer. These circuits adjust the threshold voltage of the latch based on the state of the previous bit, using a DFE code to determine the degree of response and a bias voltage generator to stabilize the response across different PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If input buffers are used to receive and latch data in DRAM devices, then data reception and processing capability is improved, but data latching accuracy deteriorates due to PVT variations across different devices
Solution Approach 1:
The patent implements a data feedback equalization (DFE) circuit that uses the previously latched data bit to adjust the threshold voltage of the current latch operation. The DFE circuit feeds back the previous bit state through capacitive coupling to dynamically adjust the switching threshold, compensating for PVT variations and improving data latching accuracy while maintaining high-speed data reception
Solution Approach 2:
The patent changes the threshold voltage parameter of the latch circuit dynamically based on the previous data bit state. By adjusting the threshold voltage through the DFE circuit's capacitive coupling, the system adapts to PVT variations and maintains accurate data latching across different operating conditions and device variations
2Measurement precision
If DFE circuits are added to adjust threshold voltage for better data latching, then data latching accuracy is improved, but device complexity increases
Solution Approach 1:
The DFE circuit is segmented into multiple parallel legs, where each leg processes a specific portion of the threshold adjustment. This segmentation allows the complex threshold adjustment function to be divided into simpler, parallel operations that can be implemented using standard CMOS transistors and capacitors, reducing the overall circuit complexity while maintaining accuracy
Solution Approach 2:
The DFE circuit functionality is merged with the existing input buffer and latch circuitry. The threshold adjustment is integrated into the differential latch structure by coupling the DFE capacitor to the differential nodes, combining the equalization function with the data latching operation in a unified circuit architecture
3Reliability
If DFE circuits adjust threshold voltage dynamically, then data latching accuracy across PVT variations is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by making the threshold voltage adjustment specific to each differential latch node based on its local signal conditions. The DFE circuit adjusts the threshold locally at each latch node independently, allowing the circuit to compensate for local variations without requiring global precision matching across the entire device
Solution Approach 2:
The DFE circuit uses the previously latched data bit itself as the feedback signal to adjust the current threshold. This self-service mechanism allows the circuit to automatically compensate for PVT variations using its own operational history, reducing the need for external calibration or high-precision manufacturing
Data Source
AI summary
Apparatuses, systems, and methods for input buffer data feedback equalization (DFE). An input buffer includes a DFE circuit which adjusts a threshold voltage of the input buffer based on a previously latched data bit. The DFE circuit includes a number of DFE legs coupled in parallel to a node of the input buffer. Each DFE leg is selectively activated by a DFE code. Each DFE leg includes a capacitance (e.g., a field effect transistor) which is coupled to the node in an active leg based on the previously latched data bit. The previously latched data bit may also be used to generate a reset signal which couples the capacitors to ground. Each DFE leg may also include a transistor coupled to a bias voltage, which is stable across a range of PVT variations.