Synchronous Input Buffer Control for DQS Reset Timing
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Solution Overview
Problem
Truncated input buffer disable periods in memory devices cause partial reset of the DQS clock generator, leading to memory failures by dropping input bits due to asynchronous behavior.
Innovation Solution
Implementing at least partially synchronous input buffer control circuitry with two ripple counters to ensure a minimum reset pulse duration for data and DQS input buffers, using a simplified 2's complement algorithm to set the start point for counter rollover and skip additional counts, thereby ensuring deterministic buffer enable/disable behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input buffer is disabled to save power during separation between write commands, then power consumption is reduced, but the DQS clock generator may not fully reset leading to partial reset conditions and memory failures
Solution Approach 1:
The patent implements a counter mechanism that counts clock cycles during the input buffer disable period. When the counter reaches a predetermined value corresponding to a minimum safe disable duration, the input buffer is re-enabled. This preliminary counting action ensures the DQS clock generator has sufficient time to fully reset before the next write command, preventing partial reset conditions while maintaining power savings during adequate separation periods.
2Productivity
If the input buffer disable period is shortened to increase command throughput, then productivity is improved, but the DQS clock generator may not fully reset causing data bits to be dropped
Solution Approach 1:
The patent employs a feedback mechanism where the counter continuously monitors the duration of the input buffer disable period. The counter value provides feedback to the control logic, which decides whether to re-enable the input buffer based on whether the minimum safe duration has been reached. This feedback loop ensures data integrity by preventing re-enablement too soon, while still allowing maximum throughput by minimizing the disable period to the necessary minimum.
3Device complexity
If asynchronous input buffer enable circuitry is used to simplify control logic, then device complexity is reduced, but unpredictable behavior occurs during truncated disable periods
Solution Approach 1:
The patent introduces a counter as an intermediary element between the asynchronous input buffer enable circuitry and the clock generator reset mechanism. The counter mediates the timing relationship by providing a measurable, synchronous reference for when the disable period has been sufficient. This intermediary allows the asynchronous circuitry to remain simple while the counter ensures predictable, reliable behavior by enforcing a minimum safe duration before re-enabling the input buffer.
Data Source
AI summary
A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.