Input Buffer Linearity Using Frequency-Dependent Impedance
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Solution Overview
Problem
Existing input buffers face challenges in achieving high-linearity and low output impedance, particularly in the low-frequency region, due to the need for large input transistors which increase noise and parasitic capacitors, and the use of small resistors that suppress loop gain and output impedance.
Innovation Solution
A flipped voltage follower is configured in a pseudo-differential architecture with a frequency-dependent impedance circuit, including capacitors and resistors, to maintain low output impedance and high loop gain across all frequencies, enabling effective high-to-low resistance transformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If large input transistors are used to reduce output impedance, then output impedance is improved, but noise and parasitic capacitors increase
Solution Approach 1:
The patent divides the single large input transistor into multiple smaller transistors (first input transistor and second input transistor) connected in parallel. This segmentation maintains the required low output impedance while reducing noise and parasitic effects compared to a single large transistor
Solution Approach 2:
The patent applies different characteristics to different parts of the circuit - the input transistors operate in strong inversion for low noise, while the output transistors operate in moderate inversion for optimal speed and impedance matching. Each component is optimized for its specific function
2Object-affected harmful factors
If small resistors are used to reduce output impedance, then output impedance is improved, but loop gain is suppressed
Solution Approach 1:
The patent uses dynamic biasing with separate bias circuits for input and output transistors. The bias voltages are adjusted to maintain optimal operating points that balance loop gain and output impedance dynamically, rather than using fixed small resistors
Solution Approach 2:
The patent changes the operating parameters of the transistors - input transistors operate in strong inversion while output transistors operate in moderate inversion. This parameter optimization allows achieving low output impedance without the need for small resistors that would suppress loop gain
3Manufacturing precision
If large input transistors are used to achieve high linearity, then linearity is improved, but parasitic capacitors increase
Solution Approach 1:
The patent segments the input stage into multiple smaller transistors that provide equivalent or better linearity through their combined operation, while generating less parasitic capacitance than a single large transistor would produce
Solution Approach 2:
The patent implements feedback mechanisms that compensate for non-linearities and parasitic effects, allowing the use of smaller transistors while maintaining high linearity performance
Data Source
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AI summary
An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.