Differential Input Buffer Offset Cancellation Without Input Mismatch
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Solution Overview
Problem
Existing high-speed digital communication systems face challenges in canceling offset voltage in differential input buffers due to manufacturing tolerances and component aging, particularly in MOS systems, where common solutions require large resistors or multicollector PNP transistors and fail to adapt to changes over time.
Innovation Solution
A system and method that introduces an offset cancellation circuit at the differential outputs of the first differential amplification stage using a differential output transistor pair with controlled DC input voltage, employing a compensation mechanism with current-control networks and voltage multiplexers to determine and adjust compensation currents based on feedback, allowing for real-time calibration and adaptation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a termination resistor is used between differential inputs to match impedance, then input return-loss constraints are satisfied, but offset voltage cancellation becomes difficult
Solution Approach 1:
The patent introduces an intermediary offset cancellation circuit that operates at the output of the differential amplifier rather than directly at the inputs. This intermediary approach allows offset cancellation without interfering with the termination resistor's impedance matching function at the inputs.
Solution Approach 2:
Instead of applying offset cancellation at the input端 (the conventional approach), the patent inverts the approach by applying cancellation at the output端 of the differential amplifier. This reversal allows the termination resistor to perform its impedance matching function without being disrupted by offset cancellation circuitry.
2Manufacturing precision
If MOS device size is enlarged to reduce manufacturing offset, then offset voltage decreases, but input return-loss constraints are violated
Solution Approach 1:
The patent extracts the offset cancellation function from the input buffer stage and places it at the output stage. This separation allows the input MOS devices to be sized according to return-loss requirements without being constrained by offset voltage considerations.
Solution Approach 2:
An intermediary offset cancellation circuit is introduced at the output stage, acting as a mediator that corrects offset voltage without affecting the input stage's impedance characteristics and return-loss performance.
3Manufacturing precision
If prior-art offset cancellation methods are used, then offset voltage is corrected, but circuit area increases due to large resistors or fuse-selected resistor strings
Solution Approach 1:
The patent replaces the mechanical/resistive offset cancellation approach (using large resistors or fuse-selected resistor strings) with an active electronic approach using transistors and current sources. This substitution dramatically reduces the circuit area while maintaining offset correction capability.
Solution Approach 2:
The patent changes the fundamental parameters of the offset cancellation circuit from passive resistive elements to active transistor-based current sources. This parameter change enables compact implementation while providing precise offset control through current modulation.
4Manufacturing precision
If fixed offset cancellation is implemented at system startup, then initial offset is compensated, but aging-induced offset changes are not addressed
Solution Approach 1:
The patent transforms the offset cancellation system from a static, fixed configuration to a dynamic, adjustable one. The offset cancellation currents can be modified in real-time through control signals, enabling the system to adapt to aging-induced changes and maintain performance over time.
Solution Approach 2:
The patent implements feedback mechanisms that allow the offset cancellation circuit to monitor and adjust its operation based on actual system performance. This feedback enables continuous compensation for aging effects and maintains optimal offset cancellation throughout the system's operational life.
Data Source
AI summary
A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input.