Input Buffer Pull-Up Timing to Prevent Pulse Width Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing input circuits for semiconductor integrated circuit devices experience significant delay times and errors in pulse width due to the short-circuiting of power supply and low-side drive elements when the input signal transitions from high to low, leading to increased delay times and pulse width errors.
Innovation Solution
The proposed input circuit incorporates a pull-up circuit with a P-type transistor configuration that prevents short-circuiting by making the power supply and input node conductive only during signal transitions from low to high, reducing delay times and maintaining the integrity of the pulse width by ensuring the power supply and low-side drive element are not short-circuited during transitions from high to low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a P-type transistor is coupled between the input node and power supply to speed up signal rise, then the delay time for signal rise is reduced, but the power supply and low-side drive element are short-circuited during signal fall, increasing delay time for signal fall
Solution Approach 1:
The patent applies the dynamics principle by making the pull-up circuit's conductivity dynamic rather than static. The P-type transistor's gate is controlled by a control signal that changes its conductivity state based on the input signal transition direction. During rising transitions, the pull-up circuit is activated to speed up the rise; during falling transitions, it is deactivated to prevent short-circuiting and maintain accurate pulse width. This dynamic control resolves the contradiction by adapting the circuit behavior to the specific transition phase.
Solution Approach 2:
The patent implements periodic action through the alternating activation and deactivation of the pull-up circuit based on the periodic nature of digital signal transitions. The control signal periodically enables the P-type transistor during rising edges and disables it during falling edges, creating a rhythm of conductive and non-conductive states that optimizes performance for each transition type while preventing harmful short-circuits.
2Speed
If the pull-up circuit makes power supply and input node conductive during signal rise, then inversion is quickly performed, but during signal fall the short-circuit slows down transition and delays inversion
Solution Approach 1:
The dynamics principle is applied by dynamically controlling the pull-up circuit's conductivity based on the direction of signal transition. The control signal ensures the P-type transistor is conductive only during rising transitions to accelerate them, and non-conductive during falling transitions to allow natural fast discharge through the low-side drive element. This dynamic switching eliminates the delay time difference between rise and fall transitions.
Data Source
AI summary
An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.