Differential Input Buffer Circuit for Noise-Distorted PWM Signals

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Solution Overview

Problem

Noise introduced at the input of drive circuits due to parasitics and other sources distorts input PWM signals, leading to corruption of drive signals in power switch applications.

Innovation Solution

An input buffer circuit comprising an input divider network, threshold generator, and comparator is used to provide a stepped-down differential input signal with adjustable thresholds, reducing signal distortion by using an overcompensated RC network and AC coupling to propagate signals quickly to comparators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If noise is introduced at the input to the drive circuit from parasitics or other sources, then the input PWM signal is distorted, but the drive signal becomes corrupted

Engineering Contradiction:
Improvesignal integrityVSAvoidnoise distortion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An input buffer circuit is introduced as an intermediary component between the PWM signal source and the drive circuit. This buffer includes a differential input stage with RC networks that actively filter and condition the signal, preventing noise from parasitics and other sources from distorting the PWM signal while maintaining signal integrity through the drive circuit

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The input buffer circuit employs feedback mechanisms where the differential input stage monitors the input signal conditions and adjusts the signal path accordingly. The RC networks provide frequency-dependent feedback that enhances noise rejection at critical frequencies while preserving the PWM signal characteristics, thereby preventing signal corruption

Inventive Principle:
Principle #23Feedback

2Reliability

If a buffer circuit is added to reduce signal distortion, then signal integrity improves, but circuit complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The input buffer circuit is designed to perform multiple functions within a single integrated stage: differential signal conditioning, noise filtering through RC networks, impedance matching, and level shifting. This multi-functionality reduces the need for separate discrete components, thereby limiting the increase in overall circuit complexity while achieving improved signal integrity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The buffer circuit merges the RC filtering networks directly into the differential input stage, combining signal conditioning and noise rejection functions in a unified structure. This integration approach minimizes the number of separate components and interconnections required, thereby reducing the complexity increase that would normally accompany the addition of a buffer circuit

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250300641A1Input buffer circuit
Publication Date: 2025.09.25 TEXAS INSTRUMENTS INC
  • US20250300641A1 patent drawing
  • US20250300641A1 patent drawing
  • US20250300641A1 patent drawing

AI summary

An example circuit includes an input divider network, a threshold generator, and a comparator. The input divider network has a first divider input, a second divider input, a first threshold input, a second threshold input, a first divider output, and a second divider output, in which the second divider input is coupled to a signal ground terminal. The threshold generator has first and second threshold outputs and a selection input, in which the first threshold output is coupled to the first threshold input and the second threshold output is coupled to the second threshold input. The comparator has first and second comparator inputs and a comparator output, in which the first comparator input is coupled to first divider output, the second comparator input is coupled to the second divider output, and the comparator output is coupled to the selection input.