Input Buffer Circuit with Voltage Boosting for Fast Latch Operation
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Solution Overview
Problem
Conventional semiconductor memory input buffer circuits face challenges in achieving fast operation and accommodating a wide range of input signals, particularly due to slower voltage increase speeds of input transistors when data input and reference voltages are high, leading to incomplete amplification and latch operations.
Innovation Solution
The proposed solution involves an input buffer circuit design that includes transistors with control circuits and inverters, allowing for intermediate voltage management and amplification completion independent of data input and reference voltage levels, ensuring efficient amplification and latch operations by configuring driving currents and precharging mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the data input signal DQ and reference voltage VREF are increased to accommodate wide voltage range (up to 42%*VDD), then the adaptability of input receiver circuit is improved, but the input transistors cannot be driven fast enough due to smaller VGS
Solution Approach 1:
A voltage boosting circuit is introduced as an intermediary between the input transistors and the power supply voltage. This circuit actively boosts the voltage at the source nodes of the input transistors during the amplification phase, effectively increasing the VGS voltage difference without requiring higher input signal voltages. The boosting circuit uses controlled current sources and switching transistors to create a virtual higher voltage potential, allowing fast transistor switching while maintaining compatibility with the full input voltage range (10%-42% of VDD).
Solution Approach 2:
The invention dynamically changes the operating parameters of the input transistors by actively controlling the source node voltages through the boosting circuit. During amplification, the source voltages are lowered (or the effective supply voltage is raised) to maximize VGS and switching speed. During precharge, the source voltages are raised to VDD to prepare for the next cycle. This parameter modulation allows the circuit to achieve high speed operation across the entire input voltage range without being constrained by the fixed input signal voltage levels.
2Adaptability or versatility
If the voltage of data input signal DQ and reference voltage VREF become higher, then the input buffer can handle higher voltage signals, but the amplification and latch operation cannot be completed within the clock cycle due to slower voltage increase speed
Solution Approach 1:
The voltage boosting circuit acts as a mediator that decouples the amplification speed from the input voltage level. By actively managing the source node voltages, the circuit ensures that the voltage difference Vdiff develops rapidly across the transistors regardless of the absolute input voltage levels. The boosting circuit uses controlled current mirrors and switching networks to accelerate the voltage transition at the internal nodes, ensuring complete amplification and latch operation within each clock cycle even when processing high voltage signals up to 42% of VDD.
Solution Approach 2:
The circuit performs preliminary precharging of the internal nodes during the low phase of the clock signal, preparing the capacitive nodes for rapid voltage transitions during the amplification phase. This preliminary action ensures that when the amplification phase begins, the nodes are already in an optimal state to quickly respond to the input voltage difference, reducing the time required to complete the amplification and latch operations within the clock cycle.
3Device complexity
If conventional input buffer design is used, then the circuit structure is simple, but the operation speed is insufficient and power consumption is high due to incomplete amplification requiring multiple cycles
Solution Approach 1:
The voltage boosting circuit is integrated into the input buffer architecture as a compact intermediary block that works in conjunction with the existing differential amplifier and latch structures. The boosting circuit uses shared transistors and controlled current sources that can be implemented with minimal additional area. By actively controlling the source node voltages, the circuit achieves complete single-cycle amplification and latching, eliminating the need for multiple clock cycles and reducing overall power consumption despite the added circuit complexity.
Data Source
AI summary
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.