Input Capacitance Modeling for VLSI Circuit Design
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Solution Overview
Problem
Current methods for designing very-large scale integration (VLSI) microelectronic circuits are inefficient due to the need for extensive re-layout and re-extraction of circuit designs after adjustments, which are time-consuming and often result in inaccurate estimates of circuit performance, particularly when adjusting transistor dimensions for improved performance.
Innovation Solution
A method and system for accurately calculating input capacitance of transistor components using input capacitance models, allowing for quick simulation of circuit performance changes without full re-layout, by associating pins with virtual nets and generating input capacitance model equations to estimate the effect of dimension alterations on circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full re-layout and re-extraction are performed after adjusting transistor dimensions, then circuit performance accuracy is improved, but design time and computational resources are significantly increased
Solution Approach 1:
The patent segments the circuit analysis into two parts: (1) components whose dimensions are unchanged can reuse their extracted parameters, and (2) only components with altered dimensions require re-extraction. This segmentation allows the design system to avoid redundant extraction of unchanged components while maintaining accuracy for modified components.
Solution Approach 2:
The patent performs preliminary identification of which components have dimension changes before initiating full re-extraction. By pre-processing the design to detect dimension alterations, the system prepares a targeted list of components requiring re-extraction, avoiding unnecessary full-circuit re-extraction and reducing overall design time.
2Measurement precision
If full re-layout and re-extraction are performed after adjusting transistor dimensions, then circuit performance accuracy is improved, but computational resources are significantly increased
Solution Approach 1:
The patent segments the extraction process to apply computational resources only to components with dimension changes. By dividing the circuit into modified and unmodified components, the system concentrates computational effort where needed, reducing overall resource consumption while maintaining extraction accuracy for affected components.
Solution Approach 2:
The patent applies partial extraction action by performing re-extraction only on the subset of components whose dimensions changed, rather than extracting all components. This partial action approach uses the minimum necessary computational resources to achieve accurate performance predictions for the modified design.
3Loss of time
If estimation methods are used for circuit performance, then design time is reduced, but accuracy becomes highly inaccurate and may be pessimistic or optimistic
Solution Approach 1:
The patent introduces an intermediary approach that combines elements of both full extraction and estimation. It uses targeted extraction for modified components as an intermediary step between rough estimation and complete re-extraction, providing sufficiently accurate results for design decisions without the full computational cost of complete extraction.
Solution Approach 2:
The patent changes the extraction parameter from 'all components' to 'only components with dimension changes'. This parameter modification allows the system to maintain acceptable accuracy for performance prediction while significantly reducing the computational burden compared to full re-extraction.
Data Source
AI summary
Implementations of the present disclosure involve methods and systems for modeling input capacitance for a component of an electronic circuit design to accurately and quickly analyze the performance of the circuit. In particular, the methods and systems may provide for an estimated input capacitance for one or more transistor components of the circuit. To determine the estimated input capacitance of a transistor, a computing system may obtain technical information about the circuit and determine one or more virtual nets that include connections between the adjusted transistor and other transistors (or other components) of the circuit design. This information may be utilized by the computing system to calculate an estimated input capacitance for the adjusted transistor of the circuit design. The calculated input capacitance of the transistor may be added into a simple simulation of the circuit design to obtain one or more operational parameters or circuit performance characteristics.


