Level-Shifting Input Circuit for Faster Falling-Edge Propagation
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Solution Overview
Problem
Conventional semiconductor integrated circuits experience signal propagation delays due to the gate voltage of the signal transfer transistor falling when the input signal falls, as the voltage clamping operation of diode-connected transistors stops at certain points, leading to inevitable delays.
Innovation Solution
The input circuit incorporates a first NMOS transistor and two PMOS transistors with differing drive capabilities, where the second PMOS transistor with higher drive capability maintains the gate voltage of the first NMOS transistor at the power supply voltage when the input signal falls, reducing propagation delay by ensuring the voltage remains constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a diode-connected NMOS transistor and high-resistive element are used to hold gate voltage, then the gate voltage is held constant to power supply voltage, but signal propagation delay increases when input signal falls
Solution Approach 1:
The patent applies dynamics by making the PMOS transistor's drive capability adjustable based on operating conditions. The second PMOS transistor has higher drive capability than the first, and this dynamic adjustment allows the circuit to respond differently to rising versus falling input signals, reducing propagation delay during signal falls while maintaining voltage stability during rises.
Solution Approach 2:
The patent changes the parameter of drive capability by using two PMOS transistors with different drive capabilities. The second PMOS transistor is designed with higher drive capability (larger width-to-length ratio) to specifically address the propagation delay issue during signal falls, while the first PMOS transistor maintains normal operation during signal rises.
2Reliability
If diode-connected transistors are used for voltage clamping, then voltage clamping operation occurs at certain points, but gate voltage inevitably falls causing propagation delay
Solution Approach 1:
The patent applies local quality by assigning different drive capabilities to different PMOS transistors for different local conditions. The first PMOS transistor handles normal voltage clamping during signal rises, while the second PMOS transistor with higher drive capability specifically addresses the local issue of gate voltage collapse during signal falls.
Solution Approach 2:
The second PMOS transistor with higher drive capability is prepared in advance to counteract the inevitable gate voltage fall during signal falls. This preliminary action ensures that when the input signal falls, the gate voltage is quickly restored, preventing propagation delay before it occurs.
3Speed
If the gate voltage is held constant during signal rise, then high-speed operation is achieved, but propagation delay occurs during signal fall
Solution Approach 1:
The patent makes the voltage holding capability dynamic by using two PMOS transistors with different drive capabilities. During signal rises, the first PMOS transistor allows flexible voltage changes for high-speed operation. During signal falls, the second PMOS transistor with higher drive capability quickly restores the gate voltage, making the overall system response dynamic and condition-dependent.
Data Source
AI summary
In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).