Input Circuit Power Reduction via Differential Amplification
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Solution Overview
Problem
The existing input circuits for semiconductor apparatuses have high power consumption due to the requirement of three resistances, which increases the overall power consumption and can lead to variations in signal potential and reference voltage.
Innovation Solution
The input circuit design includes a first buffer circuit, a capacitor, and differential amplification circuits with specific resistance connections to reduce power consumption by optimizing the voltage gain and impedance ratios, allowing for lower power usage while maintaining the same chip size and signal processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three resistances are used for impedance and offset voltage adjustment, then the input circuit can maintain proper signal levels and impedance matching, but the power consumption increases and external reference voltage terminals experience current flow variations
Solution Approach 1:
The patent extracts the DC biasing function from the traditional three-resistance configuration and implements it separately using dedicated bias circuits. This allows the main signal path resistances to be minimized for low power consumption while separate bias circuits provide the necessary DC level adjustment without affecting signal performance
Solution Approach 2:
The patent segments the impedance adjustment and offset voltage adjustment functions into separate circuit blocks. Impedance adjustment is handled by buffer circuit output resistances while offset voltage adjustment is performed by dedicated DC bias circuits, allowing each function to be optimized independently for power efficiency
2Reliability
If three resistances are used for offset voltage adjustment, then the center voltage can be adjusted, but current flows through external reference voltage terminals causing voltage variations
Solution Approach 1:
The patent introduces intermediate DC bias circuits as mediators between the buffer circuit output and the external reference voltage terminals. These bias circuits provide the necessary DC level adjustment while isolating the reference voltage terminals from direct current flow, preventing voltage variations at the terminals
Solution Approach 2:
The patent extracts the DC biasing function from the main signal path and implements it through separate bias circuits. This separation allows the reference voltage terminals to maintain stable voltages while DC adjustment is performed through dedicated circuits that do not draw current from the reference terminals
Data Source
AI summary
An input circuit includes a first differential amplification circuit receiving input from a first power source and an output of a first buffer circuit to output to an input of the first buffer circuit, a second differential amplification circuit receiving input from a second external power source and an output of a second buffer circuit to output to an input of the second buffer circuit, a first resistance coupled between the output of the first differential amplification circuit and the input of the first buffer circuit, and a second resistance coupled between the output of the second differential amplification circuit and the input of the first buffer circuit. The first resistance and the second resistance are arranged at symmetric positions to a node on a signal line from the input signal terminal to the output signal terminal.