Input Circuit Segmentation for 3D Semiconductor Direct Access Testing
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Solution Overview
Problem
Existing semiconductor systems with a system on chip (SOC) structure face challenges in directly accessing semiconductor memory modules due to non-exposed normal input terminals, requiring separate configurations for testing and operation.
Innovation Solution
An input circuit with a first and second input buffer, a switching unit, comparison unit, and storage unit is implemented, allowing for direct access and testing through test input terminals while performing normal mode operations via direct access and normal mode circuits, respectively, using a package substrate and interposer configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bumps are packaged internally in SOC configuration, then integration degree is improved, but direct access to memory modules becomes difficult
Solution Approach 1:
The input circuit is segmented into two separate input buffers: a first input buffer for test mode operation and a second input buffer for normal operation. This segmentation allows independent access paths - the first buffer can be accessed directly through test input terminals while the second buffer operates through normally packaged bumps, thus maintaining integration while enabling direct access for testing purposes
Solution Approach 2:
A switching unit acts as an intermediary between the first and second input buffers. This switching mechanism enables flexible signal routing - during test mode, signals can be routed from test input terminals through the switching unit to the second input buffer, allowing direct access testing without disrupting the normal packaged structure. During normal operation, the switching unit routes signals through the appropriate buffer, maintaining standard functionality
2Reliability
If separate test configuration is added for direct access, then testing capability is improved, but device complexity increases
Solution Approach 1:
The first input buffer and associated test circuitry are designed with multi-functionality to reduce overall complexity. The same test input terminals and first input buffer infrastructure can be used for various testing operations including direct access testing, boundary scanning, and other diagnostic functions. This universal test architecture avoids the need for separate dedicated test circuits for each function, thereby improving testing capability while limiting the increase in device complexity
Solution Approach 2:
The test mode circuitry is merged with the normal operation circuitry through the switching unit and shared input buffer architecture. Rather than implementing completely separate test and operational paths, the patent combines both functions into a unified structure where the switching unit dynamically configures the signal flow based on operational mode. This merging approach enables testing capability while minimizing the additional complexity introduced by test features
Data Source
AI summary
An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal.