Semiconductor Input Circuit Pin Skew Compensation
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in synchronously latching data signals due to pin skew, which can result in erroneous data values due to insufficient setup and hold times, caused by variations in delay quantities among comparator components in input circuits.
Innovation Solution
Incorporating a time constant adjusting circuit within the comparator of the input circuit to adjust the delay quantity, allowing for synchronization of rising edges and reduction of pin skew by modifying the time constant between the load circuit and intermediate nodes, thereby ensuring data signals reach the latch within the allowable timing and frequency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a data signal is clock synchronously latched in the semiconductor integrated circuit, then the data signal can be processed with proper timing, but pin skew causes variations in delay quantities among comparator components resulting in erroneous data values
Solution Approach 1:
The patent adjusts the time constant of the comparator circuit by changing the resistance value of a resistor connected between the intermediate node and reference potential. This parameter change compensates for delays in data signal paths, ensuring that rising edges from multiple pins arrive at the latch circuit simultaneously, thereby resolving the pin skew issue while maintaining reliable data latching
2Reliability
If the rising edges of data signals from multiple pins are synchronized, then pin skew is reduced and data integrity is improved, but additional circuit components and complexity are introduced
Solution Approach 1:
The patent introduces time constant adjusting circuits selectively at specific comparator locations where delay compensation is needed, rather than uniformly across all comparators. This localized approach synchronizes rising edges while minimizing overall circuit complexity by only adding components where necessary to address pin skew
Data Source
AI summary
In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.