Input Voltage Clamp With Signal Splitting to Reduce Clipping Loss
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Solution Overview
Problem
Conventional input voltage clamps in integrated circuits suffer from significant loss of input signals due to clipping, leading to duty cycle distortion and threshold voltage offset, especially when shifting high voltage IO signals to lower nominal voltage levels.
Innovation Solution
The integrated circuit employs a voltage splitting and clamping circuit with p-channel and n-channel pass gates and keepers, a transmission gate circuit for rail-to-rail signaling, and a digitization and clamping circuit using a Schmitt trigger comparator to split and digitize input signals, ensuring minimal signal loss and reducing duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional NMOS pass gate transistor is used to clamp input voltage, then the input signal voltage is clipped down to the nominal voltage level, but a substantial portion of the input signal is lost
Solution Approach 1:
The voltage clamping function is segmented into multiple specialized transistors: a first clamp transistor for clamping the first output signal and a second clamp transistor for clamping the second output signal. Each transistor is optimized for its specific voltage range, preventing signal loss while maintaining reliable voltage clamping to the nominal level.
Solution Approach 2:
Different transistors are assigned different local qualities based on their function: the first clamp transistor operates in the first voltage range with optimized characteristics, while the second clamp transistor operates in the second voltage range with different optimized characteristics. This local optimization ensures minimal signal loss in each operating region while achieving overall voltage clamping reliability.
2Adaptability or versatility
If voltage clamping is applied to shift down high voltage IO signals, then backward compatibility is maintained, but duty cycle distortion and threshold voltage offset occur
Solution Approach 1:
The system dynamically switches between different clamp transistors based on the input voltage range. The first clamp transistor is activated when the input signal is in the first voltage range, and the second clamp transistor is activated when the input signal is in the second voltage range. This dynamic adaptation maintains duty cycle accuracy by ensuring the appropriate transistor handles each voltage level, while still providing backward compatibility through voltage clamping.
3Device complexity
If a single NMOS pass gate is used for voltage clamping, then the circuit structure is simple, but signal integrity is severely impacted
Solution Approach 1:
The single NMOS pass gate is segmented into multiple specialized clamp transistors, each responsible for a specific voltage range. This segmentation improves signal integrity by preventing the signal loss that occurs in a single-transistor design, while the overall circuit structure remains relatively simple through the use of parallel transistor configurations.
Data Source
AI summary
An integrated circuit with input voltage clamping circuitry for receiving an input signal from external devices is provided. The input voltage clamping circuitry may include a voltage splitting and clamping circuit, a selectively enabled transmission gate circuit, and a digitization and clamping circuit. The voltage splitting and clamping circuit may be configured to split the input signal into at least two separate components each of which is limited to a predetermined voltage swing. The transmission gate circuit may be selectively enabled to provide full rail signaling when the input signal has a power supply level that is below a predefined threshold. The digitization and clamping circuit may include a Schmitt trigger translation for converting the split signal components to a digitized signal that is clamped down to the predefined threshold.