Input Display Driving Circuit with Sequential Gate Activation
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Solution Overview
Problem
Input displays with amorphous silicon photo elements face voltage fluctuation issues due to shared common voltage, affecting pixel voltage control and gray value stability in readout pixels.
Innovation Solution
A driving circuit design where the pixel and photo elements are activated sequentially by different gate lines, with the pixel element connected to a common line through a storage capacitor, and the photo element connected to a readout line, ensuring asynchronous switching and minimizing voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared common voltage line is used for both pixel element and photo element, then device complexity is reduced, but voltage fluctuation occurs affecting pixel voltage control and gray value stability
Solution Approach 1:
The patent divides the previously shared common voltage line into two separate voltage supply paths: one dedicated to the pixel element and another to the photo element. This segmentation eliminates the voltage fluctuation caused by simultaneous switching of both elements, as each element receives a stable voltage independently. The segmentation resolves the technical contradiction by maintaining circuit simplicity while ensuring voltage control stability through separate voltage supply channels.
2Speed
If pixel and photo elements are activated simultaneously, then operation speed is improved, but voltage fluctuation degrades gray value stability
Solution Approach 1:
The patent implements preliminary action by activating the pixel element first through a first gate signal, establishing a stable pixel voltage before activating the photo element with a second gate signal. This sequential activation ensures that the pixel voltage is already stabilized when the photo element switches, preventing voltage fluctuations from affecting gray value precision. The preliminary activation of the pixel element resolves the contradiction by maintaining gray value stability while still achieving fast overall operation through optimized timing.
3Reliability
If sequential activation of pixel and photo elements is implemented, then voltage stability is improved, but operation time increases
Solution Approach 1:
The patent employs periodic action through a precisely timed gate signal sequence where the first gate signal for pixel activation and the second gate signal for photo element activation are applied in a regular, optimized sequence. The timing of these periodic signals is designed to minimize the total activation time while ensuring the pixel voltage stabilizes before photo element switching. This periodic gating strategy resolves the contradiction by achieving voltage stability through controlled sequencing without excessive time loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design stabilizes pixel voltage and prevents gray value fluctuations by decoupling the activation of pixel and photo elements, maintaining consistent voltage differences and improving display performance.
Implementation Method 1
the photo current generated by the photo element
Implementation Method 2
the pixel element connected to a common line through a storage capacitor
Data Source
AI summary
A driving circuit for an input display is provided. The driving circuit includes first and second data lines disposed in parallel with each other, first and second gate lines disposed in parallel with each other and intersected with the first and the second data lines, so as to form a pixel of the input display thereby, a common line disposed between the first and the second gate lines, a first switching element having a first gate electrode connected to the first gate line, a second switching element having a second gate electrode connected to the second gate line, and a third switching element connected between the common line and the second switching element and operating in a forward-bias state. The first and second gate lines operate in sequence and the first and second switching elements are respectively activated by the first and second gate lines in sequence.