Input-Limiting Switch Circuit for High-Voltage Signal Blocking
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Solution Overview
Problem
Existing switch devices, particularly bootstrap switches, face issues with passive conduction of P-type metal-oxide-semiconductor field effect transistors and leakage currents when input signal voltages exceed power voltage levels, leading to reliability concerns and ineffective signal blocking.
Innovation Solution
A switch device comprising a switch circuit and controller that generates control signals to selectively enable or disable the signal path between input and output terminals based on voltage levels, using transistors and logic gates to manage the operation of the switch circuit and prevent excessive voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a transmission gate is used to transmit control signals, then the signal transmission path can be enabled, but when the input signal voltage exceeds the power voltage level, the PMOS becomes passively conducted and cannot effectively disable the signal transmission path
Solution Approach 1:
The transmission gate is segmented into two separate switches: an NMOS switch and a PMOS switch. This segmentation allows independent control of each switch, enabling the NMOS switch to handle high-voltage input signals while the PMOS switch maintains proper switching functionality, thus resolving the passive conduction issue when input voltage exceeds power voltage level.
Solution Approach 2:
A voltage level detection circuit is introduced as an intermediary to monitor the input signal voltage level. When the input voltage exceeds the power voltage level, this intermediary triggers a control mechanism that forces the PMOS switch to turn off, preventing passive conduction and ensuring reliable signal blocking.
2Reliability
If a bootstrap switch circuit is used to mitigate PMOS passive conduction, then the signal transmission path can be effectively disabled, but when the input signal voltage exceeds the power voltage level, the voltage difference between drain/source/gate of the NMOS may exceed the power voltage, raising reliability issues
Solution Approach 1:
A voltage level detection circuit serves as an intermediary to detect when the input signal voltage exceeds the power voltage level. This intermediary triggers a control mechanism that adjusts the gate voltage of the NMOS switch, preventing the voltage difference between drain/source/gate from exceeding safe limits and thus eliminating the reliability issue.
Solution Approach 2:
The voltage level detection circuit provides feedback about the input signal voltage level to the control logic. This feedback mechanism enables dynamic adjustment of the NMOS gate voltage, ensuring that the voltage difference across the NMOS remains within safe operating boundaries even when input voltage exceeds power voltage level.
3Ease of operation
If a transmission gate is used, then signal transmission can be achieved, but parasitic PN junction in the PMOS generates leakage current that negatively influences signal blocking function
Solution Approach 1:
The harmful parasitic PN junction effect is effectively extracted or removed from the system by replacing the PMOS-based transmission gate with an NMOS-based switch. This extraction eliminates the source of leakage current while preserving the essential signal transmission and blocking functions through the NMOS switch controlled by the voltage level detection mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively turns off the switch circuit when input signal voltages exceed power voltage levels, preventing leakage currents and ensuring reliable signal blocking, while enabling or disabling the signal path as needed based on input voltage conditions.
Implementation Method 1
the bootstrap switch is implemented based on the N-type metal-oxide-semiconductor field effect transistors (NMOS), the issue of PMOS being passively conducted can be solved
Implementation Method 2
the switch controller generates the first switch control signal and the second switch control signal that are capable of turning off the switch circuit
Data Source
AI summary
A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.