Input Node Voltage Alternation in Low-Power Semiconductor Circuits
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Solution Overview
Problem
In semiconductor devices, the low power mode causes uneven voltage application to transistors, leading to mismatched operational characteristics and potential deterioration of circuit performance during normal power mode due to consistent voltage levels across nodes during repeated low power mode activations.
Innovation Solution
A semiconductor device with first and second signal control circuits that dynamically set voltages of nodes N1 and N2 to different values during successive occurrences of low power mode, using low power signals to alternate between high and low levels, thereby reducing transistor mismatch and maintaining circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If consistent voltage levels are applied to nodes during low power mode, then power consumption is reduced, but transistor operational characteristics become mismatched and circuit performance deteriorates
Solution Approach 1:
The patent applies periodic action by alternating the voltage levels at different nodes during successive low power mode occurrences. Specifically, during odd-numbered low power mode occurrences, the first node is maintained at a first voltage level while the second node is maintained at a second voltage level. During even-numbered low power mode occurrences, the voltage levels are swapped. This periodic alternation ensures that both transistors experience similar stress conditions over time, preventing mismatch while still achieving power savings during low power mode.
Solution Approach 2:
The patent changes the voltage parameters dynamically based on the occurrence number of low power mode. The control circuit monitors whether it is an odd or even occurrence and adjusts the voltage levels accordingly. This parameter change approach allows the system to transition between different voltage states (first voltage level/second voltage level vs. second voltage level/first voltage level) to balance transistor characteristics while maintaining low power operation.
2Reliability
If voltage levels are alternated during low power mode occurrences, then transistor mismatch is reduced, but control circuit complexity increases
Solution Approach 1:
The patent implements dynamics by introducing a counter that increments with each low power mode occurrence and uses the counter value to determine voltage assignment. The control circuit dynamically adjusts which node receives which voltage level based on whether the current occurrence is odd or even. This dynamic approach automates the voltage alternation process, reducing manual intervention while maintaining transistor matching.
Solution Approach 2:
The control circuit performs self-service by automatically tracking the occurrence number of low power mode events and autonomously deciding the voltage assignment without external control. The counter and control logic work together to self-manage the voltage alternation, reducing the need for complex external control mechanisms while ensuring proper transistor matching.
Data Source
AI summary
A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.