Input Receiver Circuit Using Signal Integration for Fewer Bit Errors
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Solution Overview
Problem
Conventional serial-to-parallel converters are inefficient in handling high-speed input signals due to short setup and hold times, leading to increased development and production costs, high power requirements, and susceptibility to bit errors, especially in noisy environments.
Innovation Solution
An input receiver circuit utilizing multiple integration elements, such as capacitors, to integrate and sample high-speed input signals over extended periods, allowing longer setup and hold times and reducing bit errors, with a controller managing the integration and sampling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional serial-to-parallel converters are used to process high-speed input signals, then data transmission speed can be maintained, but setup and hold times become too short leading to increased bit errors and higher power requirements
Solution Approach 1:
The patent divides the processing of high-speed input signals into multiple sequential phases using separate integration elements. Each integration element processes the signal for a longer duration, effectively segmenting the high-speed signal into multiple lower-speed output signals that can be processed with adequate setup and hold times, thereby reducing bit errors while maintaining overall data transmission speed
Solution Approach 2:
The patent introduces integration elements (capacitors) as intermediary components between the high-speed input signal and the processing logic. These integration elements accumulate charge over extended periods, acting as a buffer that allows slower logic circuits to process the data with sufficient setup and hold times without losing the high-speed data transmission capability
2Productivity
If conventional serial-to-parallel converters operate at high speeds, then data throughput is maintained, but power requirements increase
Solution Approach 1:
The patent segments the data processing into multiple parallel channels, each handling a portion of the data throughput. This allows each channel to operate at lower speeds with correspondingly lower power consumption, while the aggregate throughput across all channels maintains the required data processing capacity
Solution Approach 2:
The patent changes the operating parameters of the circuit by using integration elements that allow slower switching speeds and longer setup/hold times. This parameter change from high-speed direct processing to lower-speed integrated processing reduces dynamic power consumption while maintaining data throughput through parallel processing paths
3Speed
If shorter setup and hold times are used in conventional converters, then high-speed processing is enabled, but development and production costs increase
Solution Approach 1:
The patent uses simple, inexpensive integration elements (capacitors) that can be easily manufactured and replaced if needed. These passive components are much cheaper than high-speed specialized logic circuits, allowing the system to achieve high-speed processing capability through software-controlled sequential processing rather than expensive hardware
4Device complexity
If conventional converters use standard logic circuits, then circuit complexity is manageable, but susceptibility to noise and bit errors increases
Solution Approach 1:
The patent introduces integration elements as intermediary components that filter and smooth the input signal before it reaches the logic circuits. This integration process inherently filters out high-frequency noise, protecting the relatively simple logic circuits from noise-induced bit errors while maintaining manageable circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit enables efficient processing of high-speed input signals at lower acquisition speeds with reduced development and production efforts, lower power requirements, and improved resistance to bit errors, making it suitable for high-speed data transmission and storage applications.
Implementation Method 1
a first integration element to integrate the high-speed input signal during a first input clock interval
Data Source
AI summary
An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.