Input Receiver Wake-Up Timing for Low-Power Clock Enable
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Solution Overview
Problem
Existing input receiver circuits face challenges with high power consumption and poor noise immunity when entering or leaving a power down mode, which affects setup time, hold time, and overall system performance.
Innovation Solution
The proposed input receiver circuit includes a first input receiving unit, a second input receiving unit, a delay unit, and a logic unit, which generate and manage enable signals and wake-up signals to control the internal clock enable signal, allowing for efficient power management and improved noise immunity by turning off unnecessary components during power down and quickly responding when entering or leaving the power down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the input receiving circuit uses a simple clock enable signal transmission structure, then the device complexity is reduced, but the power consumption increases and noise immunity deteriorates
Solution Approach 1:
The input receiving circuit is divided into two separate input receiving units: a first input receiving unit that handles clock enable signal transitions and a second input receiving unit that generates enable signals based on voltage levels. This segmentation allows each unit to be optimized for its specific function, reducing overall power consumption while maintaining signal integrity and noise immunity.
2Speed
If the input receiving circuit enters power down mode quickly, then the response time is reduced, but the setup time and hold time deteriorate
Solution Approach 1:
The delay unit generates a wake-up signal in advance based on the second enable signal before the actual power down mode transition occurs. This preliminary action ensures that the first input receiving unit has sufficient setup time and hold time to properly latch the clock enable signal, while still achieving fast response time when leaving power down mode.
Solution Approach 2:
The delay unit acts as an intermediary between the second input receiving unit and the first input receiving unit. It introduces a controlled time delay to generate the wake-up signal, ensuring proper timing relationships are maintained during power down mode transitions without compromising response speed.
3Reliability
If the first input receiving unit remains on during power down mode, then the noise immunity is improved, but the power consumption increases
Solution Approach 1:
The first input receiving unit dynamically changes its operational state based on the wake-up signal. It transitions from an active state during normal operation to a power down state during power down mode, controlled by the wake-up signal generated from the delay unit. This dynamic operation reduces power consumption while maintaining noise immunity when active.
Data Source
AI summary
An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.