Semiconductor Module Input Terminal Layout for Lower Parasitic Inductance
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Solution Overview
Problem
There is a demand for energy-saving, sophisticated, and smaller electronic devices, which requires improving the performance and reducing the size of semiconductor modules, specifically to reduce parasitic inductance components.
Innovation Solution
A semiconductor module configuration with a conductive substrate and semiconductor elements, where the input terminals are offset relative to the substrate, and the conducting member forms paths for main circuit currents, reducing parasitic inductance by overlapping upper and lower arm current paths and optimizing the layout of conducting members and control terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional semiconductor module layout is used, then manufacturing is simpler, but parasitic inductance is higher
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration where upper and lower arm current paths are vertically arranged. This dimensional change allows current paths to overlap in the vertical direction, significantly reducing parasitic inductance while maintaining a compact footprint.
Solution Approach 2:
The patent merges the upper arm and lower arm current paths by positioning them to overlap vertically. The conducting members for both arms are integrated into a unified three-dimensional structure, allowing the current paths to share spatial volume and reducing the loop area, thereby reducing parasitic inductance.
2Volume of moving object
If module size is reduced, then energy-saving and compactness improve, but parasitic inductance increases
Solution Approach 1:
By utilizing the vertical dimension for stacking upper and lower arm structures, the patent achieves compact horizontal footprint while maintaining effective current path routing. The three-dimensional arrangement allows reduced parasitic inductance despite small module size.
Solution Approach 2:
The patent nests the lower arm current path structure within the vertical space occupied by the upper arm current path structure. This nested three-dimensional arrangement maximizes space utilization and minimizes the horizontal footprint while keeping current paths short and overlapping.
3Object-affected harmful factors
If input terminals are offset from conductive substrate, then parasitic inductance reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent offsets input terminals in the vertical dimension relative to the conductive substrate rather than only in the horizontal plane. This three-dimensional terminal arrangement reduces parasitic inductance by creating more optimal current path geometry while distributing positioning requirements across multiple dimensions.
Data Source
AI summary
A semiconductor module includes a conductive substrate, a plurality of first semiconductor elements, and a plurality of second semiconductor elements. The conductive substrate includes a first conductive portion to which the plurality of first semiconductor elements are electrically bonded, and a second conductive portion to which the plurality of second semiconductor elements are electrically bonded. The semiconductor module further includes a first input terminal, a second input terminal, and a third input terminal that are provided near the first conductive portion. The second input terminal and the third input terminal are spaced apart from each other with the first input terminal therebetween. The first input terminal is electrically connected to the first conductive portion. A polarity of the first input terminal is set to be opposite to a polarity of each of the second input terminal and the third input terminal.