Inrush Current Suppression Circuit Using Gate Voltage Sensing
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Solution Overview
Problem
Existing inrush current suppression circuits in high-precision systems face issues with component damage due to tolerance stack-ups and inadequate voltage sensing, leading to premature load enablement and false triggering.
Innovation Solution
An inrush current suppression circuit comprising input circuitry, output circuitry, a current limiter circuit with a field effect transistor (FET), and a load enable circuit that senses the gate voltage to control current flow and enable the load only when the voltage exceeds a predetermined magnitude, using a series resistor-capacitor circuit and a comparator to manage the FET's gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timers are used to delay load enablement, then inrush current limiting time can be controlled, but component tolerance stack-ups cause premature enablement and reduce reliability
Solution Approach 1:
The patent replaces mechanical/electronic timer circuits with a voltage-based sensing mechanism. Instead of using timers that are subject to component tolerance stack-ups, the invention senses the gate voltage directly to determine when inrush current limiting is complete, eliminating timer-related reliability issues.
Solution Approach 2:
The patent implements feedback by continuously monitoring the gate voltage of the current limiter circuit. The load enable circuit senses the gate voltage and uses this feedback signal to determine the appropriate time to enable the load, ensuring accurate timing without component tolerance accumulation.
2Object-affected harmful factors
If the load is disabled during inrush limiting, then inrush current is suppressed, but voltage sensing becomes inadequate due to low voltage drop and power line noise
Solution Approach 1:
The patent uses the gate voltage of the current limiter circuit as an intermediary signal for load enablement control. Instead of sensing voltage across the inrush current suppression circuit directly (which suffers from low voltage drop and noise), the gate voltage serves as a reliable intermediary that accurately reflects the inrush current limiting state.
3Ease of manufacture
If component tolerance stack-ups are present, then manufacturing variations occur, but this leads to premature load enablement and component damage
Solution Approach 1:
The patent uses feedback from gate voltage sensing to dynamically determine load enablement timing, compensating for manufacturing variations in real-time. This feedback mechanism ensures that even with component tolerance stack-ups, the load is enabled only when inrush current limiting is truly complete.
Solution Approach 2:
The patent changes the sensing parameter from voltage across the suppression circuit to gate voltage of the current limiter. This parameter change makes the system less sensitive to component tolerance variations while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively limits inrush current for a sufficient period without component stack-ups, ensuring accurate load enablement and preventing damage by precisely controlling the FET's current flow and voltage sensing.
Implementation Method 1
The current limiter circuit includes a field effect transistor (FET) that comprises a gate terminal coupled to receive the gate voltage. The current limiter circuit is configured, based on the gate voltage, to vary current flow from the output circuitry to the load.
Implementation Method 2
The load enable circuit is coupled to the gate terminal and is configured to sense the gate voltage and supply a load enable signal when the gate voltage is equal to or exceeds a predetermined voltage magnitude.
Data Source
AI summary
A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.