Inset Bond Pad Structure for Stress-Resistant CMOS Sensor Bonding
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Solution Overview
Problem
Backside illuminated (BSI) CMOS image sensors face issues with peeling and cracking defects during bonding due to stress on the bond pad, which can lead to delamination and cracking in the conductive columns, affecting the reliability and durability of the image sensor packaging.
Innovation Solution
A pad structure with enhanced strength and bondability is implemented, where the bond pad is inset into a passivation layer, and the wires and vias are alternatingly stacked between the bond pad and the substrate, absorbing stress and reducing the likelihood of peeling and cracking defects by contacting the bond pad at a thicker top wire level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bond pad is exposed on the backside of the substrate, then bonding is simplified, but stress concentration causes peeling and cracking defects
Solution Approach 1:
A recess structure is formed around the bond pad before bonding, creating a stress-absorbing cushion that prevents peeling and cracking defects during the bonding process while maintaining bonding simplicity
2Strength
If the bond pad area is increased to improve bonding strength, then bondability is enhanced, but stress-induced cracking in conductive columns increases
Solution Approach 1:
The recess structure creates localized stress distribution around the bond pad, concentrating stress-absorbing features where needed while maintaining overall bond pad strength, preventing cracking in conductive columns
3Manufacturing precision
If the pad structure is simplified for easier manufacturing, then manufacturing precision is improved, but stress absorption capability is reduced
Solution Approach 1:
The pad structure is segmented into the bond pad region and the recess structure, allowing independent optimization of each component - the bond pad for electrical connection and the recess for stress absorption - while maintaining manufacturing precision
Data Source
AI summary
Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.


