Programmable In-Situ Test Clock Generation for At-Speed Delay Faults
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Solution Overview
Problem
Conventional fault testing methods, such as stuck-at fault models, are ineffective for detecting at-speed faults in semiconductor devices, and existing at-speed testing techniques struggle to maintain accuracy at higher clock speeds, particularly due to the difficulty in scaling test clock delays across different technologies, which reduces the accuracy of testing and fails to address critical path delay measurement.
Innovation Solution
The implementation of programmable in-situ launch and capture clock generation using an in-situ delayed clock generator, a Pulse Programmable Selection Generator, and a multiplexer to generate clocks with delay, allowing for the selection of clock sequences and adding extra wait time, enabling accurate at-speed testing across various technologies without external tester dependency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fault testing methods are used, then testing simplicity is maintained, but testing accuracy for timing-related faults deteriorates
Solution Approach 1:
The system uses in-situ test clock generation where the device under test generates its own test clocks internally, eliminating the need for external testers to provide clocks. This self-service approach enables accurate at-speed testing while reducing external testing complexity
Solution Approach 2:
The patent implements programmable delay elements that can be configured to generate launch and capture clocks with specific time relationships. By changing the delay parameter to match the device's operating speed, accurate timing fault detection is achieved without requiring complex external testing equipment
2Measurement precision
If existing in-situ test clock generation techniques are used, then external tester dependency is reduced, but testing accuracy at higher speeds deteriorates
Solution Approach 1:
The system employs programmable delay elements that can be dynamically configured to adjust the time relationship between launch and capture clocks. This dynamic adjustment capability allows the testing system to adapt to different device operating speeds, maintaining testing accuracy as device speed increases
Solution Approach 2:
By implementing programmable delay elements with configurable time delays, the system can change the clock timing parameters to match the device's operating frequency. This parameter adjustability enables accurate at-speed testing across a range of operating conditions without sacrificing precision
3Adaptability or versatility
If fixed delay clock generation is used, then device complexity is reduced, but adaptability to different technologies deteriorates
Solution Approach 1:
The patent implements a universal in-situ test clock generation system with programmable delay elements that can be configured for different technologies and device types. This multi-functional approach allows the same hardware structure to adapt to various technological nodes and device requirements through programming rather than hardware changes
Solution Approach 2:
The programmable delay elements provide dynamic configurability that allows the clock generation system to adapt to different technologies. By making the delay parameters adjustable rather than fixed, the system achieves broad technology compatibility without requiring complex hardware modifications for each technology node
4Measurement precision
If external testers are used for at-speed testing, then testing accuracy is maintained, but testing cost increases
Solution Approach 1:
The system enables the device under test to generate its own test clocks internally through in-situ clock generation with programmable delay elements. This self-service capability eliminates the need for expensive external testers to provide clock signals, reducing testing costs while maintaining the ability to perform accurate at-speed testing
Solution Approach 2:
The patent extracts the clock generation function from external testing equipment and implements it within the device under test itself. By taking out the clock generation requirement from the external tester, the system eliminates the need for costly external testing equipment while preserving testing accuracy through internal programmable clock generation
Data Source
AI summary
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.