Semiconductor Inspection Algorithm Selection via Die Layout Clips
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Solution Overview
Problem
Conventional inspection processes in the semiconductor industry face challenges in matching the appropriate inspection algorithm with specific inspection areas, leading to inefficiencies in defect detection and data transfer between inspection units and die layout clipping units.
Innovation Solution
A computer-based inspection unit and die layout clipping unit system that obtains location information of potential defects, generates a die layout clip with characterizing patterns, and specifies the appropriate inspection algorithm for the inspection area, enabling efficient inspection and reducing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional inspection processes use generic inspection algorithms for all areas, then implementation is simple, but defect detection accuracy decreases
Solution Approach 1:
The patent applies local quality by selecting different inspection algorithms based on the specific characteristics of each inspection area. The system analyzes die layout patterns (repetitive vs. non-repetitive) and automatically chooses appropriate algorithms (cell-to-cell for repetitive areas, die-to-die for non-repetitive areas), ensuring optimal defect detection accuracy for each local region rather than using a generic approach throughout.
Solution Approach 2:
The patent implements dynamics by making the inspection algorithm selection adaptive and automatic based on real-time analysis of die layout patterns. The system dynamically determines the appropriate algorithm by examining whether patterns are repetitive or non-repetitive, eliminating the need for manual configuration and enabling the inspection process to adapt to different area characteristics automatically.
2Measurement precision
If detailed die layout information is transferred between inspection units, then inspection accuracy improves, but data transfer time increases
Solution Approach 1:
The patent applies preliminary action by pre-analyzing die layout patterns and storing them in a database before the actual inspection process. When inspection is needed, the system retrieves pre-analyzed pattern information rather than transferring and analyzing raw die layout data in real-time, significantly reducing data transfer time while maintaining inspection accuracy.
Solution Approach 2:
The patent uses copying by creating simplified representations of die layout patterns (stored as die layout clips in the database) that capture essential characteristics without requiring transfer of complete detailed layout information. These copied pattern representations enable accurate algorithm selection with minimal data transfer.
Data Source
AI summary
Data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest may be received. A die layout clip may be generated in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest. The die layout clip may include information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen. The generated die layout clip may be transmitted to a semiconductor inspection unit where an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip.